rvtr/ctr_Repair
1
Fork 0
mirror of https://github.com/rvtr/ctr_Repair.git synced 2025-10-31 13:51:08 -04:00
Code Issues Actions Packages Projects Releases Wiki Activity
0d5bf9a14e
ctr_Repair/trunk/SkipFirstLaunch/idb/include/CTR_LegacyData.h
N2614 0d5bf9a14e UIG製のコードを追加 
git-svn-id: file:///Volumes/Transfer/gigaleak_20231201/2020-05-23%20-%20ctr.7z%20+%20svn_v1.068.zip/ctr/svn/ctr_Repair@651 385bec56-5757-e545-9c3a-d8741f4650f1
2012-02-22 02:25:50 +00:00

646 lines
28 KiB
C++
Raw Blame History

This file contains ambiguous Unicode characters

This file contains Unicode characters that might be confused with other characters. If you think that this is intentional, you can safely ignore this warning. Use the Escape button to reveal them.

/*---------------------------------------------------------------------------*
Project: Horizon
File: CTR_LgyData.h
Copyright (C)2010 Nintendo Co., Ltd. All rights reserved.
These coded instructions, statements, and computer programs contain
proprietary information of Nintendo of America Inc. and/or Nintendo
Company Ltd., and are protected by Federal copyright law. They may
not be disclosed to third parties or copied or duplicated in any form,
in whole or in part, without the prior written consent of Nintendo.
$Rev$
*---------------------------------------------------------------------------*/
#ifndef CTR_LGYDATA_H_
#define CTR_LGYDATA_H_
#ifdef __cplusplus
extern "C" {
#endif
namespace nn { namespace CTR {
#define NN_CTR_ROMHEADER_CORP_ID "NINTENDO "
#define NN_CTR_TITLE_NAME_MAX 12
#define NN_CTR_GAME_CODE_MAX 4
#define NN_CTR_MAKER_CODE_MAX 2
#define NN_CTR_DIGEST_SIZE_SHA1 20
#define NN_CTR_NINTENDO_LOGO_DATA_LENGTH 0x9c
#define NN_CTR_PARENTAL_CONTROL_INFO_SIZE 0x10
/*===========================================================================*
* ROM FORMAT
*===========================================================================*/
// ROM access control info
typedef struct LegacyRomAccessControl {
u32 common_client_key :1; // launcher deliver common client Key
u32 hw_aes_slot_B :1; // launcher deliver HW AES slot B setting for ES
u32 hw_aes_slot_C :1; // launcher deliver HW AES slot C setting for NAM
u32 sd_card_access :1; // sd card access control
u32 nand_access :1; // NAND access control
u32 game_card_on :1; // NANDアプリでゲームカード電源ON（ノーマルモード）
u32 shared2_file :1; // shared file in "nand:/shared2"
u32 hw_aes_slot_B_SignJPEGForLauncher :1; // launcher deliver HW AES slot B setting for Sign JPEG for Launcher
u32 game_card_nitro_mode :1; // NANDアプリでゲームカードNTR互換領域へアクセス
u32 hw_aes_slot_A_SSLClientCert :1; // launcher deliver HW AES slot A setting for SSL Client Certificate
u32 hw_aes_slot_B_SignJPEGForUser :1; // launcher deliver HW AES slot B setting for Sign JPEG for User
u32 photo_access_read :1; // "photo:" archive read-access control
u32 photo_access_write :1; // "photo:" archive write-access control
u32 sdmc_access_read :1; // "sdmc:" archive read-access control
u32 sdmc_access_write :1; // "sdmc:" archive write-access control
u32 backup_access_read :1; // CARD-backup read-access control
u32 backup_access_write :1; // CARD-backup write-access control
u32: 14;
u32 common_client_key_for_debugger_sysmenu :1; // launcher deliver common client Key
} LegacyRomAccessControl;
// ROM expansion flags
typedef struct LegacyRomExpansionFlags {
u8 codec_mode:1; // 0:NTR mode, 1:TWL mode // undeveloped
u8 agree_EULA:1; // 1: necessary agree EULA
u8 availableSubBannerFile:1; // 1: Available SubBannerFile
u8 WiFiConnectionIcon :1; // 1: WiFiConnectionをランチャーで表示
u8 DSWirelessIcon :1; // 1: DSWirelessIconをランチャーで表示
u8 rsv_d5:1;
u8 enable_nitro_whitelist_signature :1; // 1: NITROホワイトリスト署名有効フラグ
u8 developer_encrypt:1; // 1: 開発用セキュリティがかかっている場合に"1"。製品版では"0" (※TwlSDK UIG_branch/RC2以降はこちらが有効）
} LegacyRomExpansionFlags;
//---------------------------------------------------------------------------
// Section A ROM HEADER
//---------------------------------------------------------------------------
typedef struct LegacyRomHeader
{
//==========================================================
//
// NTR/TWL common
//
//==========================================================
//
// 0x000 System Reserved
//
char title_name[NN_CTR_TITLE_NAME_MAX]; // Soft title name
char game_code[NN_CTR_GAME_CODE_MAX]; // Game code
char maker_code[NN_CTR_MAKER_CODE_MAX]; // Maker code
char platform_code; // Platform code bit0: not support NTR, bit1: support TWL ( NTR_only=0x00, NTR/TWL=0x03, TWL_only=0x02 )
u8 rom_type; // Rom type
u8 rom_size; // Rom size (2のrom_size乗 Mbit: ex. 128Mbitのときrom_size = 7)
u8 reserved_A[7]; // System Reserved A ( Set ALL 0 )
u8 enable_signature:1; // enable ROM Header signature
u8 enable_aes:1; // enable AES encryption
u8 developer_encrypt_old:1; // 開発用セキュリティがかかっている場合に"1"。製品版では"0" (※TwlSDK RC plusまではこちらが有効）
u8 disable_debug:1; // デバッグ禁止フラグ
u8: 4;
u8 permit_landing_normal_jump:1; // アプリジャンプのノーマルジャンプで呼び出されることを許可する( for TWL Application Jump )
u8 permit_landing_tmp_jump:1; // アプリジャンプのTMPジャンプで呼び出されることを許可する( for TWL Application Jump )
// ※NTR体験版アプリはDSダウンロードプレイの署名しかついていないので、このフラグはNTR-ROMヘッダの0x160bytes内の領域に格納する必要がある。
u8: 4;
u8 for_korea:1; // For Korea
u8 for_china:1; // For China
u8 rom_version; // Rom version
u8 comp_arm9_boot_area:1; // Compress arm9 boot area
u8 comp_arm7_boot_area:1; // Compress arm7 boot area
u8 inspect_card:1; // Show inspect card
u8 disable_clear_memory_pad:1; // for Debugger
u8 enable_twl_rom_cache_read:1; // Enable TWL ROM cacheRead command
u8 :1; // reserved.
u8 warning_no_spec_rom_speed:1;// Warning not to specify rom speed
u8 disable_detect_pull_out:1; // Decect CARD removal by checking ROM-ID
//
// 0x020 for Static modules (Section:B)
//
// ARM9
u32 main_rom_offset; // ROM offset
void *main_entry_address; // Entry point
void *main_ram_address; // RAM address
u32 main_size; // Module size
// ARM7
u32 sub_rom_offset; // ROM offset
void *sub_entry_address; // Entry point
void *sub_ram_address; // RAM address
u32 sub_size; // Module size
//
// 0x040 for File Name Table[FNT] (Section:C)
//
struct ROM_FNT *fnt_offset; // ROM offset
u32 fnt_size; // Table size
//
// 0x048 for File Allocation Table[FAT] (Section:E)
//
struct ROM_FAT *fat_offset; // ROM offset
u32 fat_size; // Table size
//
// 0x050 for Overlay Tables[OVT] (Section:D)
//
// ARM9
struct ROM_OVT *main_ovt_offset; // ROM offset
u32 main_ovt_size; // Table size
// ARM7
struct ROM_OVT *sub_ovt_offset; // ROM offset
u32 sub_ovt_size; // Table size
// 0x060 for ROM control parameter (Section:F)
u32 game_cmd_param; // Game command parameter
u32 secure_cmd_param; // Secure command parameter
u32 banner_offset; // Banner ROM offset
u16 secure_area_crc16; // Secure area CRC-16
u16 secure_cmd_latency; // Secure command latency ((param+2)*256 system cycles)
// since NITRO-SDK 2.0PR4
void *main_autoload_done; // ARM9 autoload done callback address (debug purpose)
void *sub_autoload_done; // ARM7 autoload done callback address (debug purpose)
u8 ctrl_reserved_B[8]; // Ctrl Reserved B (Set 0)
// since NITRO-SDK 2.0PR6
u32 rom_valid_size; // ROM Original Size
u32 rom_header_size; // ROM Header size
u32 main_module_param_offset; // Offset for table of ARM9 module parameters
u32 sub_module_param_offset; // Offset for table of ARM7 module parameters
// 0x090 - 0x0C0 System Reserved
u16 twl_card_normal_area_rom_offset; // undeveloped
u16 twl_card_keytable_area_rom_offset; // undeveloped
u16 nand_card_dl_area_rom_offset; // undeveloped
u16 nand_card_bk_area_rom_offset; // undeveloped
u8 nand_card_flag; // undeveloped
u8 reserved_B[39];
// 0x0C0 for NINTENDO logo data
u8 nintendo_logo[ NN_CTR_NINTENDO_LOGO_DATA_LENGTH ]; // NINTENDO logo data
u16 nintendo_logo_crc16; // CRC-16
// 0x15E ROM header CRC-16
u16 header_crc16; // ROM header CRC-16
// 0x160 - 0x180 Debugger Reserved
u8 reserved_C[32]; // Debugger Reserved (Set ALL 0)
//==========================================================
//
// TWL only
//
//==========================================================
// 0x180 - 0x190 TWL-WRAM A/B/C ARM9 configuration data
u32 main_wram_config_data[8]; // developing...
// 0x1A0 - 0x1B0 TWL-WRAM A/B/C ARM7 configuration data
u32 sub_wram_config_data[4]; // developing...
// 0x1B0 - Card Region bitmap
u32 card_region_bitmap;
// 0x1B4 - AccessControl
LegacyRomAccessControl access_control;
/* 注意： fatfs_command.c 内で 0x01b4 のアドレスを
ハードコーディングしています。 このメンバのオフセットを変更しないで下さい。 */
// 0x1B8 - ARM7-SCFG
u32 arm7_scfg_ext; // SCFG-EXT
// padding(3byte)
u8 reserved_ltd_A2[ 3 ];
// 0x1BF - TWL expansion flags
LegacyRomExpansionFlags exFlags;
// 0x1C0 for EX Static modules
//
// ARM9
u32 main_ltd_rom_offset; // ROM offset // undeveloped
u8 reserved_ltd_B[ 4 ];
void *main_ltd_ram_address; // RAM address // undeveloped //
u32 main_ltd_size; // Module size // undeveloped //
// ARM7
u32 sub_ltd_rom_offset; // ROM offset // undeveloped
void *sub_mount_info_ram_address; // ARM7 MountInfo RAM address.
void *sub_ltd_ram_address; // RAM address // undeveloped //
u32 sub_ltd_size; // Module size // undeveloped //
/* 注意： os_reset.c / crt0.HYB.c / crt0.LTD.c 内で 0x01c0 ～ 0x01e0 のアドレスを
ハードコーディングしています。 これら８つのメンバのオフセットを変更しないで下さい。 */
// 0x01E0 - 0x01E8 for NITRO digest area offset & size
u32 nitro_digest_area_rom_offset;
u32 nitro_digest_area_size;
// 0x01E8 - 0x01F0 for TWL digest area offset & size
u32 twl_digest_area_rom_offset;
u32 twl_digest_area_size;
// 0x01F0 - 0x01F8 for FS digest table1 offset & size
u32 digest1_table_offset;
u32 digest1_table_size;
// 0x01F8 - 0x0200 for FS digest table2 offset & size
u32 digest2_table_offset;
u32 digest2_table_size;
// 0x0200 - 0x0208 for FS digest config parameters
u32 digest1_block_size;
u32 digest2_covered_digest1_num;
// 0x0208 - 0x020C for TWL banner size.
u32 banner_size;
// 0x020C - 0x020E for shared2 files size
u8 shared2_file0_size; // shared2 file [0]
u8 shared2_file1_size; // shared2 file [1]
/* 注意： fatfs_command.c 内で 0x020C-0x020D のアドレスを
ハードコーディングしています。 このメンバのオフセットを変更しないで下さい。 */
// 0x020E for Agree EULA version
u8 agree_EULA_version;
// 0x020F TWL Administration flags
u8 unnecessary_rating_display:1; // レーティング表記がいらないROMのときに立てる(管理用:ランチャーでは不使用)
u8: 7;
// 0x0210 - 0x0214 for TWL rom valid size
u32 twl_rom_valid_size; // ROM Original Size
// 0x0214 - 0x0218 for shared2 files size
u8 shared2_file2_size; // shared2 file [2]
u8 shared2_file3_size; // shared2 file [3]
u8 shared2_file4_size; // shared2 file [4]
u8 shared2_file5_size; // shared2 file [5]
/* 注意： fatfs_command.c 内で 0x0214 - 0x0217 のアドレスを
ハードコーディングしています。 このメンバのオフセットを変更しないで下さい。 */
// 0x0218 - 0x0220 for TWL ltd module param offset
u32 main_ltd_module_param_offset; // Offset for table of ARM9 ltd module parameters
u32 sub_ltd_module_param_offset; // Offset for table of ARM7 ltd module parameters
// 0x0220 - 0x0230 for AES target offset & size
u32 aes_target_rom_offset;
u32 aes_target_size;
u32 aes_target2_rom_offset; // 予約
u32 aes_target2_size; // 予約
// 0x0230 - 0x0238 for TitleID
union {
u64 titleID;
// struct {
u8 titleID_Lo[ 4 ];
// u32 titleID_Hi;
// };
};
/* 注意： os_reset.c / crt0.HYB.c / crt0.LTD.c / fatfs_command.c 内で 0x0234 をハードコーディングしています。
titleID_Hi のオフセットを変更しないで下さい。 */
// 0x0238 - 0x0240 for Public & Private Save Data Size
u32 public_save_data_size;
u32 private_save_data_size;
// 0x0240 - 0x02f0 reserved.
u8 reserved_ltd_F[ 0x2f0 - 0x240 ];
// 0x02f0 - 0x0300 Parental Controls Rating Info
u8 parental_control_rating_info[ NN_CTR_PARENTAL_CONTROL_INFO_SIZE ];
// 0x0300 - 0x0378 Rom Segment Digest
u8 main_static_digest[ NN_CTR_DIGEST_SIZE_SHA1 ];
u8 sub_static_digest[ NN_CTR_DIGEST_SIZE_SHA1 ];
u8 digest2_table_digest[ NN_CTR_DIGEST_SIZE_SHA1 ];
u8 banner_digest[ NN_CTR_DIGEST_SIZE_SHA1 ];
u8 main_ltd_static_digest[ NN_CTR_DIGEST_SIZE_SHA1 ];
u8 sub_ltd_static_digest[ NN_CTR_DIGEST_SIZE_SHA1 ];
} LegacyRomHeader;
// include\nn\drivers\card\CTR\ARM946ES\extra.h を移植 ---------------------------------------------------
#define NN_CTR_SDK_128M
/* MC1 */
#define NN_CTR_REG_MI_MC1_CC_SHIFT 16
#define NN_CTR_REG_MI_MC1_CC_SIZE 16
#define NN_CTR_REG_MI_MC1_CC_MASK 0xffff0000
#define NN_CTR_REG_MI_MC1_SWP_SHIFT 15
#define NN_CTR_REG_MI_MC1_SWP_SIZE 1
#define NN_CTR_REG_MI_MC1_SWP_MASK 0x00008000
#define NN_CTR_REG_MI_MC1_SL2_STATUS_SHIFT 4
#define NN_CTR_REG_MI_MC1_SL2_STATUS_SIZE 4
#define NN_CTR_REG_MI_MC1_SL2_STATUS_MASK 0x000000f0
#define NN_CTR_REG_MI_MC1_SL2_M1_SHIFT 7
#define NN_CTR_REG_MI_MC1_SL2_M1_SIZE 1
#define NN_CTR_REG_MI_MC1_SL2_M1_MASK 0x00000080
#define NN_CTR_REG_MI_MC1_SL2_M0_SHIFT 6
#define NN_CTR_REG_MI_MC1_SL2_M0_SIZE 1
#define NN_CTR_REG_MI_MC1_SL2_M0_MASK 0x00000040
#define NN_CTR_REG_MI_MC1_SL2_CDET_SHIFT 4
#define NN_CTR_REG_MI_MC1_SL2_CDET_SIZE 1
#define NN_CTR_REG_MI_MC1_SL2_CDET_MASK 0x00000010
#define NN_CTR_REG_MI_MC1_SL1_STATUS_SHIFT 0
#define NN_CTR_REG_MI_MC1_SL1_STATUS_SIZE 4
#define NN_CTR_REG_MI_MC1_SL1_STATUS_MASK 0x0000000f
#define NN_CTR_REG_MI_MC1_SL1_M1_SHIFT 3
#define NN_CTR_REG_MI_MC1_SL1_M1_SIZE 1
#define NN_CTR_REG_MI_MC1_SL1_M1_MASK 0x00000008
#define NN_CTR_REG_MI_MC1_SL1_M0_SHIFT 2
#define NN_CTR_REG_MI_MC1_SL1_M0_SIZE 1
#define NN_CTR_REG_MI_MC1_SL1_M0_MASK 0x00000004
#define NN_CTR_REG_MI_MC1_SL1_CDET_SHIFT 0
#define NN_CTR_REG_MI_MC1_SL1_CDET_SIZE 1
#define NN_CTR_REG_MI_MC1_SL1_CDET_MASK 0x00000001
#ifndef SDK_ASM
#define NN_CTR_REG_MI_MC1_FIELD( cc, swp, sl2_status, sl2_m1, sl2_m0, sl2_cdet, sl1_status, sl1_m1, sl1_m0, sl1_cdet ) \
(u32)( \
((u32)(cc) << NN_CTR_REG_MI_MC1_CC_SHIFT) | \
((u32)(swp) << NN_CTR_REG_MI_MC1_SWP_SHIFT) | \
((u32)(sl2_status) << NN_CTR_REG_MI_MC1_SL2_STATUS_SHIFT) | \
((u32)(sl2_m1) << NN_CTR_REG_MI_MC1_SL2_M1_SHIFT) | \
((u32)(sl2_m0) << NN_CTR_REG_MI_MC1_SL2_M0_SHIFT) | \
((u32)(sl2_cdet) << NN_CTR_REG_MI_MC1_SL2_CDET_SHIFT) | \
((u32)(sl1_status) << NN_CTR_REG_MI_MC1_SL1_STATUS_SHIFT) | \
((u32)(sl1_m1) << NN_CTR_REG_MI_MC1_SL1_M1_SHIFT) | \
((u32)(sl1_m0) << NN_CTR_REG_MI_MC1_SL1_M0_SHIFT) | \
((u32)(sl1_cdet) << NN_CTR_REG_MI_MC1_SL1_CDET_SHIFT))
#endif
/* MC */
#define NN_CTR_REG_MI_MC_SWP_SHIFT 15
#define NN_CTR_REG_MI_MC_SWP_SIZE 1
#define NN_CTR_REG_MI_MC_SWP_MASK 0x8000
#define NN_CTR_REG_MI_MC_SL2_MODE_SHIFT 6
#define NN_CTR_REG_MI_MC_SL2_MODE_SIZE 2
#define NN_CTR_REG_MI_MC_SL2_MODE_MASK 0x00c0
#define NN_CTR_REG_MI_MC_SL2_CDET_SHIFT 4
#define NN_CTR_REG_MI_MC_SL2_CDET_SIZE 1
#define NN_CTR_REG_MI_MC_SL2_CDET_MASK 0x0010
#define NN_CTR_REG_MI_MC_SL1_MODE_SHIFT 2
#define NN_CTR_REG_MI_MC_SL1_MODE_SIZE 2
#define NN_CTR_REG_MI_MC_SL1_MODE_MASK 0x000c
#define NN_CTR_REG_MI_MC_SL1_CDET_SHIFT 0
#define NN_CTR_REG_MI_MC_SL1_CDET_SIZE 1
#define NN_CTR_REG_MI_MC_SL1_CDET_MASK 0x0001
#ifndef SDK_ASM
#define NN_CTR_REG_MI_MC_FIELD( swp, sl2_mode, sl2_cdet, sl1_mode, sl1_cdet ) \
(u16)( \
((u32)(swp) << NN_CTR_REG_MI_MC_SWP_SHIFT) | \
((u32)(sl2_mode) << NN_CTR_REG_MI_MC_SL2_MODE_SHIFT) | \
((u32)(sl2_cdet) << NN_CTR_REG_MI_MC_SL2_CDET_SHIFT) | \
((u32)(sl1_mode) << NN_CTR_REG_MI_MC_SL1_MODE_SHIFT) | \
((u32)(sl1_cdet) << NN_CTR_REG_MI_MC_SL1_CDET_SHIFT))
#endif
/* EXMEMCNT_L */
#define NN_CTR_REG_MI_EXMEMCNT_L_EP_SHIFT 15
#define NN_CTR_REG_MI_EXMEMCNT_L_EP_SIZE 1
#define NN_CTR_REG_MI_EXMEMCNT_L_EP_MASK 0x8000
#define NN_CTR_REG_MI_EXMEMCNT_L_EMODE_SHIFT 14
#define NN_CTR_REG_MI_EXMEMCNT_L_EMODE_SIZE 1
#define NN_CTR_REG_MI_EXMEMCNT_L_EMODE_MASK 0x4000
#define NN_CTR_REG_MI_EXMEMCNT_L_ECE2_SHIFT 13
#define NN_CTR_REG_MI_EXMEMCNT_L_ECE2_SIZE 1
#define NN_CTR_REG_MI_EXMEMCNT_L_ECE2_MASK 0x2000
#define NN_CTR_REG_MI_EXMEMCNT_L_MP_SHIFT 11
#define NN_CTR_REG_MI_EXMEMCNT_L_MP_SIZE 1
#define NN_CTR_REG_MI_EXMEMCNT_L_MP_MASK 0x0800
#define NN_CTR_REG_MI_EXMEMCNT_L_MP_A_SHIFT 11
#define NN_CTR_REG_MI_EXMEMCNT_L_MP_A_SIZE 1
#define NN_CTR_REG_MI_EXMEMCNT_L_MP_A_MASK 0x0800
#define NN_CTR_REG_MI_EXMEMCNT_L_MP_B_SHIFT 10
#define NN_CTR_REG_MI_EXMEMCNT_L_MP_B_SIZE 1
#define NN_CTR_REG_MI_EXMEMCNT_L_MP_B_MASK 0x0400
#define NN_CTR_REG_MI_EXMEMCNT_L_CP_SHIFT 7
#define NN_CTR_REG_MI_EXMEMCNT_L_CP_SIZE 1
#define NN_CTR_REG_MI_EXMEMCNT_L_CP_MASK 0x0080
#define NN_CTR_REG_MI_EXMEMCNT_L_PHI_SHIFT 5
#define NN_CTR_REG_MI_EXMEMCNT_L_PHI_SIZE 2
#define NN_CTR_REG_MI_EXMEMCNT_L_PHI_MASK 0x0060
#define NN_CTR_REG_MI_EXMEMCNT_L_ROM2nd_SHIFT 4
#define NN_CTR_REG_MI_EXMEMCNT_L_ROM2nd_SIZE 1
#define NN_CTR_REG_MI_EXMEMCNT_L_ROM2nd_MASK 0x0010
#define NN_CTR_REG_MI_EXMEMCNT_L_ROM1st_SHIFT 2
#define NN_CTR_REG_MI_EXMEMCNT_L_ROM1st_SIZE 2
#define NN_CTR_REG_MI_EXMEMCNT_L_ROM1st_MASK 0x000c
#define NN_CTR_REG_MI_EXMEMCNT_L_RAM_SHIFT 0
#define NN_CTR_REG_MI_EXMEMCNT_L_RAM_SIZE 2
#define NN_CTR_REG_MI_EXMEMCNT_L_RAM_MASK 0x0003
#ifndef SDK_ASM
#define NN_CTR_REG_MI_EXMEMCNT_L_FIELD( ep, emode, ece2, mp, mp_a, mp_b, cp, phi, rom2nd, rom1st, ram ) \
(u16)( \
((u32)(ep) << NN_CTR_REG_MI_EXMEMCNT_L_EP_SHIFT) | \
((u32)(emode) << NN_CTR_REG_MI_EXMEMCNT_L_EMODE_SHIFT) | \
((u32)(ece2) << NN_CTR_REG_MI_EXMEMCNT_L_ECE2_SHIFT) | \
((u32)(mp) << NN_CTR_REG_MI_EXMEMCNT_L_MP_SHIFT) | \
((u32)(mp_a) << NN_CTR_REG_MI_EXMEMCNT_L_MP_A_SHIFT) | \
((u32)(mp_b) << NN_CTR_REG_MI_EXMEMCNT_L_MP_B_SHIFT) | \
((u32)(cp) << NN_CTR_REG_MI_EXMEMCNT_L_CP_SHIFT) | \
((u32)(phi) << NN_CTR_REG_MI_EXMEMCNT_L_PHI_SHIFT) | \
((u32)(rom2nd) << NN_CTR_REG_MI_EXMEMCNT_L_ROM2nd_SHIFT) | \
((u32)(rom1st) << NN_CTR_REG_MI_EXMEMCNT_L_ROM1st_SHIFT) | \
((u32)(ram) << NN_CTR_REG_MI_EXMEMCNT_L_RAM_SHIFT))
#endif
/* EXMEMCNT_H */
#define NN_CTR_REG_MI_EXMEMCNT_H_PHI33M_SHIFT 7
#define NN_CTR_REG_MI_EXMEMCNT_H_PHI33M_SIZE 1
#define NN_CTR_REG_MI_EXMEMCNT_H_PHI33M_MASK 0x0080
#define NN_CTR_REG_MI_EXMEMCNT_H_WW1_2nd_SHIFT 5
#define NN_CTR_REG_MI_EXMEMCNT_H_WW1_2nd_SIZE 1
#define NN_CTR_REG_MI_EXMEMCNT_H_WW1_2nd_MASK 0x0020
#define NN_CTR_REG_MI_EXMEMCNT_H_WW1_1st_SHIFT 3
#define NN_CTR_REG_MI_EXMEMCNT_H_WW1_1st_SIZE 2
#define NN_CTR_REG_MI_EXMEMCNT_H_WW1_1st_MASK 0x0018
#define NN_CTR_REG_MI_EXMEMCNT_H_WW0_2nd_SHIFT 2
#define NN_CTR_REG_MI_EXMEMCNT_H_WW0_2nd_SIZE 1
#define NN_CTR_REG_MI_EXMEMCNT_H_WW0_2nd_MASK 0x0004
#define NN_CTR_REG_MI_EXMEMCNT_H_WW0_1st_SHIFT 0
#define NN_CTR_REG_MI_EXMEMCNT_H_WW0_1st_SIZE 2
#define NN_CTR_REG_MI_EXMEMCNT_H_WW0_1st_MASK 0x0003
#ifndef SDK_ASM
#define NN_CTR_REG_MI_EXMEMCNT_H_FIELD( phi33m, ww1_2nd, ww1_1st, ww0_2nd, ww0_1st ) \
(u16)( \
((u32)(phi33m) << NN_CTR_REG_MI_EXMEMCNT_H_PHI33M_SHIFT) | \
((u32)(ww1_2nd) << NN_CTR_REG_MI_EXMEMCNT_H_WW1_2nd_SHIFT) | \
((u32)(ww1_1st) << NN_CTR_REG_MI_EXMEMCNT_H_WW1_1st_SHIFT) | \
((u32)(ww0_2nd) << NN_CTR_REG_MI_EXMEMCNT_H_WW0_2nd_SHIFT) | \
((u32)(ww0_1st) << NN_CTR_REG_MI_EXMEMCNT_H_WW0_1st_SHIFT))
#endif
#define NN_CTR_AES_KEY_SIZE 16 // 128 bit
#define NN_CTR_GAME_CODE_MAX 4
#define NN_CTR_AES_BLOCK_SIZE 16
// define NN_CTR_data---------------------------------------------
#define NN_CTR_BANNER_IMAGE_SIZE (32 * 32 / (8/4))
#define NN_CTR_BANNER_PLTT_SIZE (16 * 2)
#define NN_CTR_BANNER_LANG_LENGTH 128
#define NN_CTR_BANNER_LANG_SIZE (BANNER_LANG_LENGTH * 2)
#define NN_CTR_BANNER_VER_NTR_MIN 1 // NTRバナーver.MIN.
#define NN_CTR_BANNER_VER_NTR_MAX 3 // NTRバナーver.MAX.(smaller than UCHAR_MAX)
#define NN_CTR_BANNER_VER_TWL_MIN 3 // TWLバナーver.MIN.
#define NN_CTR_BANNER_VER_TWL_MAX 3 // TWLバナーver.MAX.(smaller than UCHAR_MAX)
#define NN_CTR_BANNER_CHINESE_SUPPORT_VER 2 // 中国語サポートver.
#define NN_CTR_BANNER_KOREAN_SUPPORT_VER 3 // 韓国語サポートver.
#define NN_CTR_BANNER_LANG_NUM_RSV 8 // 言語予約領域数
#define NN_CTR_BANNER_ANIME_PATTERN_NUM 8 // バナーアニメパターン数
#define NN_CTR_BANNER_ANIME_CONTROL_INFO_NUM 64 // バナーアニメコントロール情報数
// バナーファイル上の言語配置順序
typedef enum {
NN_CTR_BANNER_PRIO_JAPANESE = 0,
NN_CTR_BANNER_PRIO_ENGLISH,
NN_CTR_BANNER_PRIO_FRENCH,
NN_CTR_BANNER_PRIO_GERMAN,
NN_CTR_BANNER_PRIO_ITALIAN,
NN_CTR_BANNER_PRIO_SPANISH,
NN_CTR_BANNER_PRIO_CHINESE,
NN_CTR_BANNER_PRIO_KOREAN,
NN_CTR_BANNER_LANG_NUM,
NN_CTR_BANNER_LANG_NUM_V1 = NN_CTR_BANNER_PRIO_CHINESE,
NN_CTR_BANNER_LANG_NUM_V2 = NN_CTR_BANNER_PRIO_KOREAN - NN_CTR_BANNER_PRIO_CHINESE,
NN_CTR_BANNER_LANG_NUM_V3 = NN_CTR_BANNER_LANG_NUM - NN_CTR_BANNER_PRIO_KOREAN
} LegacyBannerLanguagePriorityIdx;
// プラットフォームコード
typedef enum {
NN_CTR_BANNER_PLATFORM_NTR = 0,
NN_CTR_BANNER_PLATFORM_TWL = 1,
NN_CTR_BANNER_PLATFORM_MAX = 2
} LegacyBannerPlatformCode;
// バナーアニメデータ構造体(bannercvtr.exeが出力するデータ)
typedef struct {
u8 image [ NN_CTR_BANNER_ANIME_PATTERN_NUM ][ NN_CTR_BANNER_IMAGE_SIZE ];
u8 pltt [ NN_CTR_BANNER_ANIME_PATTERN_NUM ][ NN_CTR_BANNER_PLTT_SIZE ];
struct {
u8 frameCount : 8;
union {
struct {
u8 cellNo : 3;
u8 plttNo : 3;
u8 flipType : 2;
}normal;
u8 animeType;
};
} control[ NN_CTR_BANNER_ANIME_CONTROL_INFO_NUM ];
} LegacyBannerAnime;
// バナーヘッダ
typedef struct {
u8 version;
u8 platform; // 上記BannerPlatformCodeで指定
u16 crc16_v1;
u16 crc16_v2;
u16 crc16_v3;
u16 crc16_anime;
u8 reserved_B[ 22 ];
} LegacyBannerHeader;
// バナーver.1 ボディ
typedef struct {
u8 image[ NN_CTR_BANNER_IMAGE_SIZE ];
u8 pltt[ NN_CTR_BANNER_PLTT_SIZE ];
u16 gameName[ NN_CTR_BANNER_LANG_NUM_V1 ][ NN_CTR_BANNER_LANG_LENGTH ];
} LegacyBannerFileV1;
// バナーver.2 ボディ追加分
typedef struct {
u16 gameName[ NN_CTR_BANNER_LANG_NUM_V2 ][ NN_CTR_BANNER_LANG_LENGTH ];
} LegacyBannerFileV2;
// バナーver.3 ボディ追加分
typedef struct {
u16 gameName[ NN_CTR_BANNER_LANG_NUM_V3 ][ NN_CTR_BANNER_LANG_LENGTH ];
} LegacyBannerFileV3;
// バナーgameName 言語拡張予約領域
typedef struct {
u16 gameName[ NN_CTR_BANNER_LANG_NUM_RSV ][ NN_CTR_BANNER_LANG_LENGTH ];
} LegacyBannerFileRsv;
// TWLバナーファイル構造体
typedef struct {
LegacyBannerHeader h;
LegacyBannerFileV1 v1;
LegacyBannerFileV2 v2;
LegacyBannerFileV3 v3; // <--- ここまではNTRバナーと共通
LegacyBannerFileRsv rsv;
LegacyBannerAnime anime;
} LegacyTwlBannerFile;
}
}
#ifdef __cplusplus
}
#endif
#endif //CTR_LGYDATA_H_
Reference in New Issue View Git Blame Copy Permalink