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https://github.com/rvtr/TwlIPL_commit-99.git
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90 lines
3.5 KiB
C
90 lines
3.5 KiB
C
/*---------------------------------------------------------------------------*
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Project: TwlFirm - tools - makenandfirm
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File: wram_regs.c
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Copyright 2007 Nintendo. All rights reserved.
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These coded instructions, statements, and computer programs contain
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proprietary information of Nintendo of America Inc. and/or Nintendo
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Company Ltd., and are protected by Federal copyright law. They may
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not be disclosed to third parties or copied or duplicated in any form,
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in whole or in part, without the prior written consent of Nintendo.
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$Date:: 2007-09-06$
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$Rev$
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$Author$
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*---------------------------------------------------------------------------*/
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#include <twl/mi.h>
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#include <firm/format/wram_regs.h>
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MIHeader_WramRegs wram_regs =
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{
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// ARM9
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{
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REG_WRAM_A_BNK_PACK(0, MI_WRAM_A_ARM7, MI_WRAM_A_OFS_0KB, TRUE),
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REG_WRAM_A_BNK_PACK(1, MI_WRAM_A_ARM7, MI_WRAM_A_OFS_64KB, TRUE),
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REG_WRAM_A_BNK_PACK(2, MI_WRAM_A_ARM7, MI_WRAM_A_OFS_128KB, TRUE),
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REG_WRAM_A_BNK_PACK(3, MI_WRAM_A_ARM7, MI_WRAM_A_OFS_192KB, TRUE),
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},
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{
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REG_WRAM_B_BNK_PACK(0, MI_WRAM_B_ARM7, MI_WRAM_B_OFS_0KB, TRUE),
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REG_WRAM_B_BNK_PACK(1, MI_WRAM_B_ARM7, MI_WRAM_B_OFS_32KB, TRUE),
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REG_WRAM_B_BNK_PACK(2, MI_WRAM_B_ARM7, MI_WRAM_B_OFS_64KB, TRUE),
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REG_WRAM_B_BNK_PACK(3, MI_WRAM_B_ARM7, MI_WRAM_B_OFS_96KB, TRUE),
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REG_WRAM_B_BNK_PACK(4, MI_WRAM_B_ARM7, MI_WRAM_B_OFS_128KB, TRUE),
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REG_WRAM_B_BNK_PACK(5, MI_WRAM_B_ARM7, MI_WRAM_B_OFS_160KB, TRUE),
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REG_WRAM_B_BNK_PACK(6, MI_WRAM_B_ARM7, MI_WRAM_B_OFS_192KB, TRUE),
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REG_WRAM_B_BNK_PACK(7, MI_WRAM_B_ARM7, MI_WRAM_B_OFS_224KB, TRUE),
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},
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{
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REG_WRAM_C_BNK_PACK(0, MI_WRAM_C_ARM9, MI_WRAM_C_OFS_0KB, TRUE),
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REG_WRAM_C_BNK_PACK(1, MI_WRAM_C_ARM9, MI_WRAM_C_OFS_32KB, TRUE),
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REG_WRAM_C_BNK_PACK(2, MI_WRAM_C_ARM9, MI_WRAM_C_OFS_64KB, TRUE),
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REG_WRAM_C_BNK_PACK(3, MI_WRAM_C_ARM9, MI_WRAM_C_OFS_96KB, TRUE),
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REG_WRAM_C_BNK_PACK(4, MI_WRAM_C_ARM9, MI_WRAM_C_OFS_128KB, TRUE),
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REG_WRAM_C_BNK_PACK(5, MI_WRAM_C_ARM9, MI_WRAM_C_OFS_160KB, TRUE),
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REG_WRAM_C_BNK_PACK(6, MI_WRAM_C_ARM9, MI_WRAM_C_OFS_192KB, TRUE),
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REG_WRAM_C_BNK_PACK(7, MI_WRAM_C_ARM9, MI_WRAM_C_OFS_224KB, TRUE),
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},
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REG_WRAM_A_MAP_PACK(MI_WRAM_MAP_NULL,
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MI_WRAM_MAP_NULL,
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MI_WRAM_A_IMG_128KB
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),
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REG_WRAM_B_MAP_PACK(MI_WRAM_MAP_NULL,
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MI_WRAM_MAP_NULL,
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MI_WRAM_B_IMG_128KB
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),
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REG_WRAM_C_MAP_PACK(HW_WRAM_AREA_HALF,
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HW_WRAM_AREA_HALF + 0x00020000,
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MI_WRAM_C_IMG_128KB
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),
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// ARM7
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REG_WRAM_A_MAP_PACK(HW_WRAM_AREA_HALF,
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HW_WRAM_AREA_HALF + 0x00020000,
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MI_WRAM_A_IMG_128KB
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),
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REG_WRAM_B_MAP_PACK(HW_WRAM_AREA_HALF + 0x00020000,
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HW_WRAM_AREA_HALF + 0x00040000,
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MI_WRAM_B_IMG_128KB
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),
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REG_WRAM_C_MAP_PACK(MI_WRAM_MAP_NULL,
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MI_WRAM_MAP_NULL,
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MI_WRAM_C_IMG_128KB
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),
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// WRAM Lock
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{
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0,
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0,
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0,
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},
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// WRAM-0/1
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MI_WRAM_ARM7_ALL,
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// VRAM-C
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7,
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// VRAM-D
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7,
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};
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