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git-svn-id: file:///Users/lillianskinner/Downloads/platinum/twl/TwlIPL/trunk@659 b08762b0-b915-fc4b-9d8c-17b2551a87ff
131 lines
5.2 KiB
C
131 lines
5.2 KiB
C
/*---------------------------------------------------------------------------*
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Project: TwlIPL - wram_regs
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File: wram_regs.c
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Copyright 2007 Nintendo. All rights reserved.
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These coded instructions, statements, and computer programs contain
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proprietary information of Nintendo of America Inc. and/or Nintendo
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Company Ltd., and are protected by Federal copyright law. They may
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not be disclosed to third parties or copied or duplicated in any form,
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in whole or in part, without the prior written consent of Nintendo.
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$Date:: 2007-12-11#$
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$Rev: 2990 $
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$Author: nakasima $
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*---------------------------------------------------------------------------*/
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#include <twl/mi.h>
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#define HW_HYENA_WRAM_A_OFS (HW_WRAM_A_LTD - HW_WRAM_BASE)
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#define HW_HYENA_WRAM_A_OFS_END (HW_WRAM_A_LTD_END - HW_WRAM_BASE)
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#define HW_HYENA_WRAM_B_OFS (HW_HYENA_WRAM_A_OFS - HW_WRAM_B_SIZE)
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#define HW_HYENA_WRAM_B_OFS_END (HW_HYENA_WRAM_A_OFS)
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#define HW_HYENA_WRAM_C_OFS (HW_HYENA_WRAM_B_OFS - HW_WRAM_C_SIZE)
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#define HW_HYENA_WRAM_C_OFS_END (HW_HYENA_WRAM_B_OFS)
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// MAP_TS_LTD for hyena
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// WRAM-A Lock:ON, Master:ARM7, Enable:Slot0-3(256Kbytes), Address(7):0x037c0000-0x037fffff, Address(9):None
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// WRAM-B Lock:ON, Master:ARM7, Enable:Slot7 (32Kbytes), Address(7):0x037b8000-0x037bffff, Address(9):None
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// WRAM-B Lock:OFF, Master:ARM9, Enable:Slot0-6(224Kbytes), Address(7):0x03780000-0x037b7fff, Address(9):0x03780000-0x037bffff
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// WRAM-C Lock:OFF, Msster:ARM9, Enable:Slot0-7(256Kbytes), Address(7):0x03740000-0x0377ffff, Address(9):0x03740000-0x0377ffff
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// WRAM-0 Master:ARM9, (16Kbytes), Address(7):0x03040000-0x03043fff, Address(9):0x03040000-0x03043fff
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// WRAM-1 Master:ARM9, (16Kbytes), Address(7):0x03044000-0x03047fff, Address(9):0x03044000-0x03047fff
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// MAP_TS_LTD original
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// WRAM-A Lock:ON, Master:ARM7, Enable:Slot0-3(256Kbytes), Address(7):0x037c0000-0x037fffff, Address(9):None
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// WRAM-B Lock:OFF, Master:ARM9, Enable:Slot0-7(256Kbytes), Address(7):0x03900000-0x0393ffff, Address(9):0x03900000-0x0393ffff
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// WRAM-C Lock:OFF, Msster:ARM9, Enable:Slot0-7(256Kbytes), Address(7):0x03940000-0x0397ffff, Address(9):0x03940000-0x0397ffff
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// WRAM-0 Master:ARM9, (16Kbytes), Address(7):0x03040000-0x03043fff, Address(9):0x03040000-0x03043fff
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// WRAM-1 Master:ARM9, (16Kbytes), Address(7):0x03044000-0x03047fff, Address(9):0x03044000-0x03047fff
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u32 HYENA_WramReg[0x30/sizeof(u32)] =
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{
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// ARM9
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// WRAM-A
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REG_MI_MBK1_FIELD(
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TRUE, MI_WRAM_OFFSET_192KB/2, MI_WRAM_ARM7,
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TRUE, MI_WRAM_OFFSET_128KB/2, MI_WRAM_ARM7,
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TRUE, MI_WRAM_OFFSET_64KB/2, MI_WRAM_ARM7,
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TRUE, MI_WRAM_OFFSET_0KB/2, MI_WRAM_ARM7
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),
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// WRAM-B
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REG_MI_MBK2_FIELD(
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TRUE, MI_WRAM_OFFSET_96KB, MI_WRAM_ARM9,
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TRUE, MI_WRAM_OFFSET_64KB, MI_WRAM_ARM9,
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TRUE, MI_WRAM_OFFSET_32KB, MI_WRAM_ARM9,
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TRUE, MI_WRAM_OFFSET_0KB, MI_WRAM_ARM9
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),
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#if 0
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REG_MI_MBK3_FIELD(
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TRUE, MI_WRAM_OFFSET_224KB, MI_WRAM_ARM7,
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TRUE, MI_WRAM_OFFSET_192KB, MI_WRAM_ARM9,
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TRUE, MI_WRAM_OFFSET_160KB, MI_WRAM_ARM9,
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TRUE, MI_WRAM_OFFSET_128KB, MI_WRAM_ARM9
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),
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#else
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REG_MI_MBK3_FIELD(
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TRUE, MI_WRAM_OFFSET_224KB, MI_WRAM_ARM7,
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TRUE, MI_WRAM_OFFSET_192KB, MI_WRAM_ARM7,
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TRUE, MI_WRAM_OFFSET_160KB, MI_WRAM_ARM7,
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TRUE, MI_WRAM_OFFSET_128KB, MI_WRAM_ARM7
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),
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#endif
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// WRAM-C
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REG_MI_MBK4_FIELD(
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TRUE, MI_WRAM_OFFSET_96KB, MI_WRAM_ARM9,
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TRUE, MI_WRAM_OFFSET_64KB, MI_WRAM_ARM9,
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TRUE, MI_WRAM_OFFSET_32KB, MI_WRAM_ARM9,
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TRUE, MI_WRAM_OFFSET_0KB, MI_WRAM_ARM9
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),
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REG_MI_MBK5_FIELD(
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TRUE, MI_WRAM_OFFSET_224KB, MI_WRAM_ARM9,
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TRUE, MI_WRAM_OFFSET_192KB, MI_WRAM_ARM9,
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TRUE, MI_WRAM_OFFSET_160KB, MI_WRAM_ARM9,
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TRUE, MI_WRAM_OFFSET_128KB, MI_WRAM_ARM9
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),
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REG_MI_MBK6_FIELD( NULL >> 16,
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MI_WRAM_IMAGE_256KB,
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NULL >> 16
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),
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REG_MI_MBK7_FIELD( HW_HYENA_WRAM_B_OFS_END >> 15,
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MI_WRAM_IMAGE_256KB,
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HW_HYENA_WRAM_B_OFS >> 15
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),
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REG_MI_MBK8_FIELD( HW_HYENA_WRAM_C_OFS_END >> 15,
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MI_WRAM_IMAGE_256KB,
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HW_HYENA_WRAM_C_OFS >> 15
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),
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// ARM7
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REG_MI_MBK6_FIELD( HW_HYENA_WRAM_A_OFS_END >> 16,
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MI_WRAM_IMAGE_256KB,
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HW_HYENA_WRAM_A_OFS >> 16
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),
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REG_MI_MBK7_FIELD( HW_HYENA_WRAM_B_OFS_END >> 15,
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MI_WRAM_IMAGE_256KB,
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HW_HYENA_WRAM_B_OFS >> 15
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),
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REG_MI_MBK8_FIELD( HW_HYENA_WRAM_C_OFS_END >> 15,
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MI_WRAM_IMAGE_256KB,
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HW_HYENA_WRAM_C_OFS >> 15
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),
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// WRAM Lock
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(u32)(
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(0x0F << 0) |
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(0x80 << 8) |
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(0x00 << 16) |
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// WRAM-0/1
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(0 << 24) |
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// VRAM-C
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(7 << 26) |
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// VRAM-D
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(7 << 29)
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),
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};
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