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git-svn-id: file:///Users/lillianskinner/Downloads/platinum/twl/TwlIPL/trunk@1900 b08762b0-b915-fc4b-9d8c-17b2551a87ff
534 lines
22 KiB
C
534 lines
22 KiB
C
/*---------------------------------------------------------------------------*
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Project: TwlIPL - tests - DisplaySystemInformation
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File: myIoreg_SCFG.h
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Copyright 2007 Nintendo. All rights reserved.
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These coded instructions, statements, and computer programs contain
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proprietary information of Nintendo of America Inc. and/or Nintendo
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Company Ltd., and are protected by Federal copyright law. They may
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not be disclosed to third parties or copied or duplicated in any form,
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in whole or in part, without the prior written consent of Nintendo.
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*---------------------------------------------------------------------------*/
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// ARM9側で受け取ったARM7のSCFGを参照するために
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// ARM9側なのにARM7依存のオフセット情報が必要...
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// マクロ再定義を防ぐための苦肉の策
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#ifndef __MY_IOREG_SCFG_H__
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#define __MY_IOREG_SCFG_H__
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*
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* Definition of Register offsets, addresses and variables.
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*/
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/* ROM */
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#define DISP_REG_ROM_OFFSET 0x4000
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#define DISP_REG_ROM_ADDR (HW_REG_BASE + DISP_REG_ROM_OFFSET)
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/* A9ROM */
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#define DISP_REG_A9ROM_OFFSET 0x4000
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#define DISP_REG_A9ROM_ADDR (HW_REG_BASE + DISP_REG_A9ROM_OFFSET)
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/* A7ROM */
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#define DISP_REG_A7ROM_OFFSET 0x4001
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#define DISP_REG_A7ROM_ADDR (HW_REG_BASE + DISP_REG_A7ROM_OFFSET)
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/* ROMWE */
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#define DISP_REG_ROMWE_OFFSET 0x4002
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#define DISP_REG_ROMWE_ADDR (HW_REG_BASE + DISP_REG_ROMWE_OFFSET)
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/* CLK */
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#define DISP_REG_CLK_OFFSET 0x4004
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#define DISP_REG_CLK_ADDR (HW_REG_BASE + DISP_REG_CLK_OFFSET)
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/* JTAG */
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#define DISP_REG_JTAG_OFFSET 0x4006
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#define DISP_REG_JTAG_ADDR (HW_REG_BASE + DISP_REG_JTAG_OFFSET)
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/* EXT */
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#define DISP_REG_EXT_OFFSET 0x4008
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#define DISP_REG_EXT_ADDR (HW_REG_BASE + DISP_REG_EXT_OFFSET)
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/* MC */
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#define DISP_REG_MC_OFFSET 0x4010
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#define DISP_REG_MC_ADDR (HW_REG_BASE + DISP_REG_MC_OFFSET)
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/* MCCHAT */
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#define DISP_REG_MCCHAT_OFFSET 0x4012
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#define DISP_REG_MCCHAT_ADDR (HW_REG_BASE + DISP_REG_MCCHAT_OFFSET)
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/* MC2 */
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#define DISP_REG_MC2_OFFSET 0x4014
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#define DISP_REG_MC2_ADDR (HW_REG_BASE + DISP_REG_MC2_OFFSET)
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/* WL */
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#define DISP_REG_WL_OFFSET 0x4020
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#define DISP_REG_WL_ADDR (HW_REG_BASE + DISP_REG_WL_OFFSET)
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/* OP */
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#define DISP_REG_OP_OFFSET 0x4024
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#define DISP_REG_OP_ADDR (HW_REG_BASE + DISP_REG_OP_OFFSET)
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/*
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* Definitions of Register fields
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*/
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/* ROM */
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#define DISP_REG_SCFG_ROM_ROMWE_SHIFT 16
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#define DISP_REG_SCFG_ROM_ROMWE_SIZE 1
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#define DISP_REG_SCFG_ROM_ROMWE_MASK 0x00010000
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#define DISP_REG_SCFG_ROM_ARM7FUSE_SHIFT 10
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#define DISP_REG_SCFG_ROM_ARM7FUSE_SIZE 1
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#define DISP_REG_SCFG_ROM_ARM7FUSE_MASK 0x00000400
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#define DISP_REG_SCFG_ROM_ARM7RSEL_SHIFT 9
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#define DISP_REG_SCFG_ROM_ARM7RSEL_SIZE 1
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#define DISP_REG_SCFG_ROM_ARM7RSEL_MASK 0x00000200
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#define DISP_REG_SCFG_ROM_ARM7SEL_SHIFT 8
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#define DISP_REG_SCFG_ROM_ARM7SEL_SIZE 1
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#define DISP_REG_SCFG_ROM_ARM7SEL_MASK 0x00000100
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#define DISP_REG_SCFG_ROM_ARM9RSEL_SHIFT 1
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#define DISP_REG_SCFG_ROM_ARM9RSEL_SIZE 1
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#define DISP_REG_SCFG_ROM_ARM9RSEL_MASK 0x00000002
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#define DISP_REG_SCFG_ROM_ARM9SEL_SHIFT 0
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#define DISP_REG_SCFG_ROM_ARM9SEL_SIZE 1
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#define DISP_REG_SCFG_ROM_ARM9SEL_MASK 0x00000001
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#ifndef SDK_ASM
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#define DISP_REG_SCFG_ROM_FIELD( romwe, arm7fuse, arm7rsel, arm7sel, arm9rsel, arm9sel ) \
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(u32)( \
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((u32)(romwe) << DISP_REG_SCFG_ROM_ROMWE_SHIFT) | \
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((u32)(arm7fuse) << DISP_REG_SCFG_ROM_ARM7FUSE_SHIFT) | \
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((u32)(arm7rsel) << DISP_REG_SCFG_ROM_ARM7RSEL_SHIFT) | \
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((u32)(arm7sel) << DISP_REG_SCFG_ROM_ARM7SEL_SHIFT) | \
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((u32)(arm9rsel) << DISP_REG_SCFG_ROM_ARM9RSEL_SHIFT) | \
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((u32)(arm9sel) << DISP_REG_SCFG_ROM_ARM9SEL_SHIFT))
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#endif
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/* A9ROM */
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#define DISP_REG_SCFG_A9ROM_RSEL_SHIFT 1
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#define DISP_REG_SCFG_A9ROM_RSEL_SIZE 1
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#define DISP_REG_SCFG_A9ROM_RSEL_MASK 0x02
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#define DISP_REG_SCFG_A9ROM_SEC_SHIFT 0
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#define DISP_REG_SCFG_A9ROM_SEC_SIZE 1
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#define DISP_REG_SCFG_A9ROM_SEC_MASK 0x01
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#ifndef SDK_ASM
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#define DISP_REG_SCFG_A9ROM_FIELD( rsel, sec ) \
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(u8)( \
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((u32)(rsel) << DISP_REG_SCFG_A9ROM_RSEL_SHIFT) | \
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((u32)(sec) << DISP_REG_SCFG_A9ROM_SEC_SHIFT))
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#endif
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/* A7ROM */
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#define DISP_REG_SCFG_A7ROM_FUSE_SHIFT 2
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#define DISP_REG_SCFG_A7ROM_FUSE_SIZE 1
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#define DISP_REG_SCFG_A7ROM_FUSE_MASK 0x04
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#define DISP_REG_SCFG_A7ROM_RSEL_SHIFT 1
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#define DISP_REG_SCFG_A7ROM_RSEL_SIZE 1
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#define DISP_REG_SCFG_A7ROM_RSEL_MASK 0x02
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#define DISP_REG_SCFG_A7ROM_SEC_SHIFT 0
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#define DISP_REG_SCFG_A7ROM_SEC_SIZE 1
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#define DISP_REG_SCFG_A7ROM_SEC_MASK 0x01
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#ifndef SDK_ASM
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#define DISP_REG_SCFG_A7ROM_FIELD( fuse, rsel, sec ) \
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(u8)( \
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((u32)(fuse) << DISP_REG_SCFG_A7ROM_FUSE_SHIFT) | \
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((u32)(rsel) << DISP_REG_SCFG_A7ROM_RSEL_SHIFT) | \
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((u32)(sec) << DISP_REG_SCFG_A7ROM_SEC_SHIFT))
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#endif
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/* ROMWE */
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#define DISP_REG_SCFG_ROMWE_WE_SHIFT 0
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#define DISP_REG_SCFG_ROMWE_WE_SIZE 1
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#define DISP_REG_SCFG_ROMWE_WE_MASK 0x0001
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#ifndef SDK_ASM
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#define DISP_REG_SCFG_ROMWE_FIELD( we ) \
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(u16)( \
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((u32)(we) << DISP_REG_SCFG_ROMWE_WE_SHIFT))
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#endif
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/* CLK */
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#define DISP_REG_SCFG_CLK_SNDMCLK_SHIFT 8
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#define DISP_REG_SCFG_CLK_SNDMCLK_SIZE 1
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#define DISP_REG_SCFG_CLK_SNDMCLK_MASK 0x0100
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#define DISP_REG_SCFG_CLK_WRAMHCLK_SHIFT 7
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#define DISP_REG_SCFG_CLK_WRAMHCLK_SIZE 1
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#define DISP_REG_SCFG_CLK_WRAMHCLK_MASK 0x0080
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#define DISP_REG_SCFG_CLK_AESHCLK_SHIFT 2
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#define DISP_REG_SCFG_CLK_AESHCLK_SIZE 1
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#define DISP_REG_SCFG_CLK_AESHCLK_MASK 0x0004
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#define DISP_REG_SCFG_CLK_SD2HCLK_SHIFT 1
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#define DISP_REG_SCFG_CLK_SD2HCLK_SIZE 1
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#define DISP_REG_SCFG_CLK_SD2HCLK_MASK 0x0002
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#define DISP_REG_SCFG_CLK_SD1HCLK_SHIFT 0
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#define DISP_REG_SCFG_CLK_SD1HCLK_SIZE 1
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#define DISP_REG_SCFG_CLK_SD1HCLK_MASK 0x0001
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#ifndef SDK_ASM
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#define DISP_REG_SCFG_CLK_FIELD( sndmclk, wramhclk, aeshclk, sd2hclk, sd1hclk ) \
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(u16)( \
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((u32)(sndmclk) << DISP_REG_SCFG_CLK_SNDMCLK_SHIFT) | \
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((u32)(wramhclk) << DISP_REG_SCFG_CLK_WRAMHCLK_SHIFT) | \
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((u32)(aeshclk) << DISP_REG_SCFG_CLK_AESHCLK_SHIFT) | \
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((u32)(sd2hclk) << DISP_REG_SCFG_CLK_SD2HCLK_SHIFT) | \
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((u32)(sd1hclk) << DISP_REG_SCFG_CLK_SD1HCLK_SHIFT))
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#endif
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/* JTAG */
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#define DISP_REG_SCFG_JTAG_DSPJE_SHIFT 8
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#define DISP_REG_SCFG_JTAG_DSPJE_SIZE 1
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#define DISP_REG_SCFG_JTAG_DSPJE_MASK 0x0100
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#define DISP_REG_SCFG_JTAG_CPUJE_SHIFT 1
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#define DISP_REG_SCFG_JTAG_CPUJE_SIZE 1
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#define DISP_REG_SCFG_JTAG_CPUJE_MASK 0x0002
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#define DISP_REG_SCFG_JTAG_ARM7SEL_SHIFT 0
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#define DISP_REG_SCFG_JTAG_ARM7SEL_SIZE 1
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#define DISP_REG_SCFG_JTAG_ARM7SEL_MASK 0x0001
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#ifndef SDK_ASM
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#define DISP_REG_SCFG_JTAG_FIELD( dspje, cpuje, arm7sel ) \
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(u16)( \
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((u32)(dspje) << DISP_REG_SCFG_JTAG_DSPJE_SHIFT) | \
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((u32)(cpuje) << DISP_REG_SCFG_JTAG_CPUJE_SHIFT) | \
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((u32)(arm7sel) << DISP_REG_SCFG_JTAG_ARM7SEL_SHIFT))
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#endif
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/* EXT */
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#define DISP_REG_SCFG_EXT_CFG_SHIFT 31
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#define DISP_REG_SCFG_EXT_CFG_SIZE 1
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#define DISP_REG_SCFG_EXT_CFG_MASK 0x80000000
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#define DISP_REG_SCFG_EXT_PUENABLE_SHIFT 28
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#define DISP_REG_SCFG_EXT_PUENABLE_SIZE 1
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#define DISP_REG_SCFG_EXT_PUENABLE_MASK 0x10000000
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#define DISP_REG_SCFG_EXT_SD20_SHIFT 28
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#define DISP_REG_SCFG_EXT_SD20_SIZE 1
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#define DISP_REG_SCFG_EXT_SD20_MASK 0x10000000
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#define DISP_REG_SCFG_EXT_NEWB_ACCESS_E_SHIFT 16
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#define DISP_REG_SCFG_EXT_NEWB_ACCESS_E_SIZE 10
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#define DISP_REG_SCFG_EXT_NEWB_ACCESS_E_MASK 0x03ff0000
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#define DISP_REG_SCFG_EXT_WRAM_SHIFT 25
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#define DISP_REG_SCFG_EXT_WRAM_SIZE 1
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#define DISP_REG_SCFG_EXT_WRAM_MASK 0x02000000
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#define DISP_REG_SCFG_EXT_MC_B_SHIFT 24
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#define DISP_REG_SCFG_EXT_MC_B_SIZE 1
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#define DISP_REG_SCFG_EXT_MC_B_MASK 0x01000000
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#define DISP_REG_SCFG_EXT_GPIO_SHIFT 23
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#define DISP_REG_SCFG_EXT_GPIO_SIZE 1
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#define DISP_REG_SCFG_EXT_GPIO_MASK 0x00800000
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#define DISP_REG_SCFG_EXT_I2C_SHIFT 22
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#define DISP_REG_SCFG_EXT_I2C_SIZE 1
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#define DISP_REG_SCFG_EXT_I2C_MASK 0x00400000
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#define DISP_REG_SCFG_EXT_I2S_SHIFT 21
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#define DISP_REG_SCFG_EXT_I2S_SIZE 1
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#define DISP_REG_SCFG_EXT_I2S_MASK 0x00200000
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#define DISP_REG_SCFG_EXT_MIC_SHIFT 20
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#define DISP_REG_SCFG_EXT_MIC_SIZE 1
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#define DISP_REG_SCFG_EXT_MIC_MASK 0x00100000
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#define DISP_REG_SCFG_EXT_SD2_SHIFT 19
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#define DISP_REG_SCFG_EXT_SD2_SIZE 1
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#define DISP_REG_SCFG_EXT_SD2_MASK 0x00080000
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#define DISP_REG_SCFG_EXT_SD1_SHIFT 18
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#define DISP_REG_SCFG_EXT_SD1_SIZE 1
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#define DISP_REG_SCFG_EXT_SD1_MASK 0x00040000
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#define DISP_REG_SCFG_EXT_AES_SHIFT 17
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#define DISP_REG_SCFG_EXT_AES_SIZE 1
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#define DISP_REG_SCFG_EXT_AES_MASK 0x00020000
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#define DISP_REG_SCFG_EXT_DMAC_SHIFT 16
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#define DISP_REG_SCFG_EXT_DMAC_SIZE 1
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#define DISP_REG_SCFG_EXT_DMAC_MASK 0x00010000
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#define DISP_REG_SCFG_EXT_NITROB_EX_E_SHIFT 8
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#define DISP_REG_SCFG_EXT_NITROB_EX_E_SIZE 8
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#define DISP_REG_SCFG_EXT_NITROB_EX_E_MASK 0x0000ff00
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#define DISP_REG_SCFG_EXT_PSRAM_SHIFT 14
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#define DISP_REG_SCFG_EXT_PSRAM_SIZE 2
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#define DISP_REG_SCFG_EXT_PSRAM_MASK 0x0000c000
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#define DISP_REG_SCFG_EXT_VRAM_SHIFT 13
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#define DISP_REG_SCFG_EXT_VRAM_SIZE 1
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#define DISP_REG_SCFG_EXT_VRAM_MASK 0x00002000
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#define DISP_REG_SCFG_EXT_LCDC_SHIFT 12
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#define DISP_REG_SCFG_EXT_LCDC_SIZE 1
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#define DISP_REG_SCFG_EXT_LCDC_MASK 0x00001000
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#define DISP_REG_SCFG_EXT_SIO_SHIFT 11
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#define DISP_REG_SCFG_EXT_SIO_SIZE 1
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#define DISP_REG_SCFG_EXT_SIO_MASK 0x00000800
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#define DISP_REG_SCFG_EXT_DSEL_SHIFT 10
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#define DISP_REG_SCFG_EXT_DSEL_SIZE 1
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#define DISP_REG_SCFG_EXT_DSEL_MASK 0x00000400
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#define DISP_REG_SCFG_EXT_SPI_SHIFT 9
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#define DISP_REG_SCFG_EXT_SPI_SIZE 1
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#define DISP_REG_SCFG_EXT_SPI_MASK 0x00000200
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#define DISP_REG_SCFG_EXT_INTC_SHIFT 8
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#define DISP_REG_SCFG_EXT_INTC_SIZE 1
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#define DISP_REG_SCFG_EXT_INTC_MASK 0x00000100
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#define DISP_REG_SCFG_EXT_NITROB_MOD_E_SHIFT 0
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#define DISP_REG_SCFG_EXT_NITROB_MOD_E_SIZE 8
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#define DISP_REG_SCFG_EXT_NITROB_MOD_E_MASK 0x000000ff
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#define DISP_REG_SCFG_EXT_MC_SHIFT 7
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#define DISP_REG_SCFG_EXT_MC_SIZE 1
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#define DISP_REG_SCFG_EXT_MC_MASK 0x00000080
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#define DISP_REG_SCFG_EXT_SND_SHIFT 2
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#define DISP_REG_SCFG_EXT_SND_SIZE 1
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#define DISP_REG_SCFG_EXT_SND_MASK 0x00000004
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#define DISP_REG_SCFG_EXT_SDMA_SHIFT 1
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#define DISP_REG_SCFG_EXT_SDMA_SIZE 1
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#define DISP_REG_SCFG_EXT_SDMA_MASK 0x00000002
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#define DISP_REG_SCFG_EXT_DMA_SHIFT 0
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#define DISP_REG_SCFG_EXT_DMA_SIZE 1
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#define DISP_REG_SCFG_EXT_DMA_MASK 0x00000001
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#ifndef SDK_ASM
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#define DISP_REG_SCFG_EXT_FIELD( cfg, puenable, sd20, newb_access_e, wram, mc_b, gpio, i2c, i2s, mic, sd2, sd1, aes, dmac, nitrob_ex_e, psram, vram, lcdc, sio, dsel, spi, intc, nitrob_mod_e, mc, snd, sdma, dma ) \
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(u32)( \
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((u32)(cfg) << DISP_REG_SCFG_EXT_CFG_SHIFT) | \
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((u32)(puenable) << DISP_REG_SCFG_EXT_PUENABLE_SHIFT) | \
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((u32)(sd20) << DISP_REG_SCFG_EXT_SD20_SHIFT) | \
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((u32)(newb_access_e) << DISP_REG_SCFG_EXT_NEWB_ACCESS_E_SHIFT) | \
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((u32)(wram) << DISP_REG_SCFG_EXT_WRAM_SHIFT) | \
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((u32)(mc_b) << DISP_REG_SCFG_EXT_MC_B_SHIFT) | \
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((u32)(gpio) << DISP_REG_SCFG_EXT_GPIO_SHIFT) | \
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((u32)(i2c) << DISP_REG_SCFG_EXT_I2C_SHIFT) | \
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((u32)(i2s) << DISP_REG_SCFG_EXT_I2S_SHIFT) | \
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((u32)(mic) << DISP_REG_SCFG_EXT_MIC_SHIFT) | \
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((u32)(sd2) << DISP_REG_SCFG_EXT_SD2_SHIFT) | \
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((u32)(sd1) << DISP_REG_SCFG_EXT_SD1_SHIFT) | \
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((u32)(aes) << DISP_REG_SCFG_EXT_AES_SHIFT) | \
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((u32)(dmac) << DISP_REG_SCFG_EXT_DMAC_SHIFT) | \
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((u32)(nitrob_ex_e) << DISP_REG_SCFG_EXT_NITROB_EX_E_SHIFT) | \
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((u32)(psram) << DISP_REG_SCFG_EXT_PSRAM_SHIFT) | \
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((u32)(vram) << DISP_REG_SCFG_EXT_VRAM_SHIFT) | \
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((u32)(lcdc) << DISP_REG_SCFG_EXT_LCDC_SHIFT) | \
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((u32)(sio) << DISP_REG_SCFG_EXT_SIO_SHIFT) | \
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((u32)(dsel) << DISP_REG_SCFG_EXT_DSEL_SHIFT) | \
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((u32)(spi) << DISP_REG_SCFG_EXT_SPI_SHIFT) | \
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((u32)(intc) << DISP_REG_SCFG_EXT_INTC_SHIFT) | \
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((u32)(nitrob_mod_e) << DISP_REG_SCFG_EXT_NITROB_MOD_E_SHIFT) | \
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((u32)(mc) << DISP_REG_SCFG_EXT_MC_SHIFT) | \
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((u32)(snd) << DISP_REG_SCFG_EXT_SND_SHIFT) | \
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((u32)(sdma) << DISP_REG_SCFG_EXT_SDMA_SHIFT) | \
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((u32)(dma) << DISP_REG_SCFG_EXT_DMA_SHIFT))
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#endif
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/* MC1 */
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#define DISP_REG_MI_MC1_CC_SHIFT 16
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#define DISP_REG_MI_MC1_CC_SIZE 16
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#define DISP_REG_MI_MC1_CC_MASK 0xffff0000
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#define DISP_REG_MI_MC1_SWP_SHIFT 15
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#define DISP_REG_MI_MC1_SWP_SIZE 1
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#define DISP_REG_MI_MC1_SWP_MASK 0x00008000
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#define DISP_REG_MI_MC1_SL2_STATUS_SHIFT 4
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#define DISP_REG_MI_MC1_SL2_STATUS_SIZE 4
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#define DISP_REG_MI_MC1_SL2_STATUS_MASK 0x000000f0
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#define DISP_REG_MI_MC1_SL2_M1_SHIFT 7
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#define DISP_REG_MI_MC1_SL2_M1_SIZE 1
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#define DISP_REG_MI_MC1_SL2_M1_MASK 0x00000080
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#define DISP_REG_MI_MC1_SL2_M0_SHIFT 6
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#define DISP_REG_MI_MC1_SL2_M0_SIZE 1
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#define DISP_REG_MI_MC1_SL2_M0_MASK 0x00000040
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#define DISP_REG_MI_MC1_SL2_CDET_SHIFT 4
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#define DISP_REG_MI_MC1_SL2_CDET_SIZE 1
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#define DISP_REG_MI_MC1_SL2_CDET_MASK 0x00000010
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#define DISP_REG_MI_MC1_SL1_STATUS_SHIFT 0
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#define DISP_REG_MI_MC1_SL1_STATUS_SIZE 4
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#define DISP_REG_MI_MC1_SL1_STATUS_MASK 0x0000000f
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#define DISP_REG_MI_MC1_SL1_M1_SHIFT 3
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#define DISP_REG_MI_MC1_SL1_M1_SIZE 1
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#define DISP_REG_MI_MC1_SL1_M1_MASK 0x00000008
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#define DISP_REG_MI_MC1_SL1_M0_SHIFT 2
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#define DISP_REG_MI_MC1_SL1_M0_SIZE 1
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#define DISP_REG_MI_MC1_SL1_M0_MASK 0x00000004
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#define DISP_REG_MI_MC1_SL1_CDET_SHIFT 0
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#define DISP_REG_MI_MC1_SL1_CDET_SIZE 1
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#define DISP_REG_MI_MC1_SL1_CDET_MASK 0x00000001
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/* MC */
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#define DISP_REG_MI_MC_SWP_SHIFT 15
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#define DISP_REG_MI_MC_SWP_SIZE 1
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#define DISP_REG_MI_MC_SWP_MASK 0x8000
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#define DISP_REG_MI_MC_SL2_MODE_SHIFT 6
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#define DISP_REG_MI_MC_SL2_MODE_SIZE 2
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#define DISP_REG_MI_MC_SL2_MODE_MASK 0x00c0
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#define DISP_REG_MI_MC_SL2_CDET_SHIFT 4
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#define DISP_REG_MI_MC_SL2_CDET_SIZE 1
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#define DISP_REG_MI_MC_SL2_CDET_MASK 0x0010
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#define DISP_REG_MI_MC_SL1_MODE_SHIFT 2
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#define DISP_REG_MI_MC_SL1_MODE_SIZE 2
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#define DISP_REG_MI_MC_SL1_MODE_MASK 0x000c
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#define DISP_REG_MI_MC_SL1_CDET_SHIFT 0
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#define DISP_REG_MI_MC_SL1_CDET_SIZE 1
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#define DISP_REG_MI_MC_SL1_CDET_MASK 0x0001
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#ifndef SDK_ASM
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#define DISP_REG_MI_MC_FIELD( swp, sl2_mode, sl2_cdet, sl1_mode, sl1_cdet ) \
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(u16)( \
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((u32)(swp) << DISP_REG_MI_MC_SWP_SHIFT) | \
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((u32)(sl2_mode) << DISP_REG_MI_MC_SL2_MODE_SHIFT) | \
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((u32)(sl2_cdet) << DISP_REG_MI_MC_SL2_CDET_SHIFT) | \
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((u32)(sl1_mode) << DISP_REG_MI_MC_SL1_MODE_SHIFT) | \
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((u32)(sl1_cdet) << DISP_REG_MI_MC_SL1_CDET_SHIFT))
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#endif
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/* MCCHAT */
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#define DISP_REG_MI_MCCHAT_CC_SHIFT 0
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#define DISP_REG_MI_MCCHAT_CC_SIZE 16
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#define DISP_REG_MI_MCCHAT_CC_MASK 0xffff
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#ifndef SDK_ASM
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#define DISP_REG_MI_MCCHAT_FIELD( cc ) \
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(u16)( \
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((u32)(cc) << DISP_REG_MI_MCCHAT_CC_SHIFT))
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#endif
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/* MC2 */
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#define DISP_REG_MI_MC2_CA_SHIFT 0
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#define DISP_REG_MI_MC2_CA_SIZE 16
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#define DISP_REG_MI_MC2_CA_MASK 0xffff
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#ifndef SDK_ASM
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#define DISP_REG_MI_MC2_FIELD( ca ) \
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(u16)( \
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((u32)(ca) << DISP_REG_MI_MC2_CA_SHIFT))
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#endif
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/* WL */
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#define DISP_REG_SCFG_WL_OFFB_SHIFT 0
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#define DISP_REG_SCFG_WL_OFFB_SIZE 1
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#define DISP_REG_SCFG_WL_OFFB_MASK 0x0001
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#ifndef SDK_ASM
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#define DISP_REG_SCFG_WL_FIELD( offb ) \
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(u16)( \
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((u32)(offb) << DISP_REG_SCFG_WL_OFFB_SHIFT))
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#endif
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/* OP */
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#define DISP_REG_SCFG_OP_OP1_SHIFT 1
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#define DISP_REG_SCFG_OP_OP1_SIZE 1
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#define DISP_REG_SCFG_OP_OP1_MASK 0x0002
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#define DISP_REG_SCFG_OP_OP0_SHIFT 0
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#define DISP_REG_SCFG_OP_OP0_SIZE 1
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#define DISP_REG_SCFG_OP_OP0_MASK 0x0001
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#define DISP_REG_SCFG_OP_OPT_SHIFT 0
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#define DISP_REG_SCFG_OP_OPT_SIZE 2
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#define DISP_REG_SCFG_OP_OPT_MASK 0x0003
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#ifndef SDK_ASM
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#define DISP_REG_SCFG_OP_FIELD( op1, op0, opt ) \
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(u16)( \
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((u32)(op1) << DISP_REG_SCFG_OP_OP1_SHIFT) | \
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((u32)(op0) << DISP_REG_SCFG_OP_OP0_SHIFT) | \
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((u32)(opt) << DISP_REG_SCFG_OP_OPT_SHIFT))
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#endif
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#ifdef __cplusplus
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} /* extern "C" */
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#endif
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/* TWL_IOREG_SCFG_H_ */
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#endif
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