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git-svn-id: file:///Users/lillianskinner/Downloads/platinum/twl/TwlIPL/trunk@3 b08762b0-b915-fc4b-9d8c-17b2551a87ff
108 lines
4.2 KiB
C
108 lines
4.2 KiB
C
/*---------------------------------------------------------------------------*
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Project: TwlFirm - tools - makegcdfirm
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File: wram_regs.c
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Copyright 2007 Nintendo. All rights reserved.
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These coded instructions, statements, and computer programs contain
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proprietary information of Nintendo of America Inc. and/or Nintendo
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Company Ltd., and are protected by Federal copyright law. They may
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not be disclosed to third parties or copied or duplicated in any form,
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in whole or in part, without the prior written consent of Nintendo.
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$Date:: 2007-09-06$
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$Rev$
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$Author$
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*---------------------------------------------------------------------------*/
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#include "format_rom.h"
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//#define SDK_ASM
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#define NITRO_TYPES_H_
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#include <twl/hw/ARM9/ioreg_MI.h>
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#include <twl/mi/common/sharedWram.h>
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#include <firm/format/wram_regs.h>
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// define macro -------------------------------------------
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#define MI_WRAM_MAP_NULL HW_WRAM_AREA
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#define REG_WRAM_MAP_CONV_ADDR( regno, abc, border, addr ) \
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( \
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((((addr) - HW_WRAM_AREA) / MI_WRAM_##abc##_SLOT_SIZE) & \
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(REG_MI_MBK##regno##_W##abc##_##border##_MASK >> \
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REG_MI_MBK##regno##_W##abc##_##border##_SHIFT)) \
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)
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// global variables----------------------------------------
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MIHeader_WramRegs wram_regs_init =
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{
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// ARM9
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{
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REG_MI_MBK_A0_FIELD( 1, MI_WRAM_OFFSET_0KB , MI_WRAM_ARM7 ),
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REG_MI_MBK_A1_FIELD( 1, MI_WRAM_OFFSET_64KB , MI_WRAM_ARM7 ),
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REG_MI_MBK_A2_FIELD( 1, MI_WRAM_OFFSET_128KB, MI_WRAM_ARM7 ),
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REG_MI_MBK_A3_FIELD( 1, MI_WRAM_OFFSET_192KB, MI_WRAM_ARM7 ),
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},
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{
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REG_MI_MBK_B0_FIELD( 1, MI_WRAM_OFFSET_0KB , MI_WRAM_ARM7 ),
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REG_MI_MBK_B1_FIELD( 1, MI_WRAM_OFFSET_32KB , MI_WRAM_ARM7 ),
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REG_MI_MBK_B2_FIELD( 1, MI_WRAM_OFFSET_64KB , MI_WRAM_ARM7 ),
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REG_MI_MBK_B3_FIELD( 1, MI_WRAM_OFFSET_96KB , MI_WRAM_ARM7 ),
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REG_MI_MBK_B4_FIELD( 1, MI_WRAM_OFFSET_128KB, MI_WRAM_ARM7 ),
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REG_MI_MBK_B5_FIELD( 1, MI_WRAM_OFFSET_160KB, MI_WRAM_ARM7 ),
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REG_MI_MBK_B6_FIELD( 1, MI_WRAM_OFFSET_192KB, MI_WRAM_ARM7 ),
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REG_MI_MBK_B7_FIELD( 1, MI_WRAM_OFFSET_224KB, MI_WRAM_ARM7 ),
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},
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{
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REG_MI_MBK_C0_FIELD( 1, MI_WRAM_OFFSET_0KB , MI_WRAM_ARM9 ),
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REG_MI_MBK_C1_FIELD( 1, MI_WRAM_OFFSET_32KB , MI_WRAM_ARM9 ),
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REG_MI_MBK_C2_FIELD( 1, MI_WRAM_OFFSET_64KB , MI_WRAM_ARM9 ),
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REG_MI_MBK_C3_FIELD( 1, MI_WRAM_OFFSET_96KB , MI_WRAM_ARM9 ),
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REG_MI_MBK_C4_FIELD( 1, MI_WRAM_OFFSET_128KB, MI_WRAM_ARM9 ),
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REG_MI_MBK_C5_FIELD( 1, MI_WRAM_OFFSET_160KB, MI_WRAM_ARM9 ),
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REG_MI_MBK_C6_FIELD( 1, MI_WRAM_OFFSET_192KB, MI_WRAM_ARM9 ),
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REG_MI_MBK_C7_FIELD( 1, MI_WRAM_OFFSET_224KB, MI_WRAM_ARM9 ),
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},
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REG_MI_MBK6_FIELD( REG_WRAM_MAP_CONV_ADDR( 6, A, EADDR, MI_WRAM_MAP_NULL ),
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MI_WRAM_IMAGE_128KB,
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REG_WRAM_MAP_CONV_ADDR( 6, A, SADDR, MI_WRAM_MAP_NULL )
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),
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REG_MI_MBK7_FIELD( REG_WRAM_MAP_CONV_ADDR( 7, B, EADDR, MI_WRAM_MAP_NULL ),
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MI_WRAM_IMAGE_128KB,
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REG_WRAM_MAP_CONV_ADDR( 7, B, SADDR, MI_WRAM_MAP_NULL )
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),
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REG_MI_MBK8_FIELD( REG_WRAM_MAP_CONV_ADDR( 8, C, EADDR, HW_WRAM_AREA_HALF + 0x00020000 ),
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MI_WRAM_IMAGE_128KB,
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REG_WRAM_MAP_CONV_ADDR( 8, C, SADDR, HW_WRAM_AREA_HALF )
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),
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// ARM7
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REG_MI_MBK6_FIELD( REG_WRAM_MAP_CONV_ADDR( 6, A, EADDR, HW_WRAM_AREA_HALF + 0x00020000 ),
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MI_WRAM_IMAGE_128KB,
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REG_WRAM_MAP_CONV_ADDR( 6, A, SADDR, HW_WRAM_AREA_HALF )
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),
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REG_MI_MBK7_FIELD( REG_WRAM_MAP_CONV_ADDR( 7, B, EADDR, HW_WRAM_AREA_HALF + 0x00040000 ),
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MI_WRAM_IMAGE_128KB,
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REG_WRAM_MAP_CONV_ADDR( 7, B, SADDR, HW_WRAM_AREA_HALF + 0x00020000 )
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),
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REG_MI_MBK8_FIELD( REG_WRAM_MAP_CONV_ADDR( 8, C, EADDR, MI_WRAM_MAP_NULL ),
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MI_WRAM_IMAGE_128KB,
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REG_WRAM_MAP_CONV_ADDR( 8, C, SADDR, MI_WRAM_MAP_NULL )
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),
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// WRAM Lock
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{
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0,
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0,
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0,
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},
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// WRAM-0/1
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3,
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// VRAM-C
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7,
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// VRAM-D
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7,
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};
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