mirror of
https://github.com/rvtr/TwlIPL.git
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291 lines
9.4 KiB
C
291 lines
9.4 KiB
C
#ifndef MISC_H_
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#define MISC_H_
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#include <time.h>
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typedef enum
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{
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FALSE = 0,
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TRUE = 1
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}
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BOOL;
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typedef unsigned char u8;
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typedef unsigned short int u16;
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typedef unsigned long int u32;
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typedef unsigned long long u64;
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typedef signed char s8;
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typedef signed short int s16;
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typedef signed long int s32;
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typedef signed long long s64;
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#endif //MISC_H_
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#if 0
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typedef struct ROM_Header_Short
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{
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//==========================================================
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//
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// NTR/TWL common
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//
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//==========================================================
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//
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// 0x000 System Reserved
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//
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char title_name[TITLE_NAME_MAX]; // Soft title name
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char game_code[GAME_CODE_MAX]; // Game code
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char maker_code[MAKER_CODE_MAX]; // Maker code
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char platform_code; // Platform code bit0: not support NTR, bit1: support TWL ( NTR_only=0x00, NTR/TWL=0x03, TWL_only=0x02 )
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u8 rom_type; // Rom type
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u8 rom_size; // Rom size (2のrom_size乗 Mbit: ex. 128Mbitのときrom_size = 7)
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u8 reserved_A[7]; // System Reserved A ( Set ALL 0 )
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u8 enable_signature:1; // enable ROM Header signature
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u8 enable_aes:1; // enable AES encryption
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u8 developer_encrypt:1; // 開発用セキュリティがかかっている場合に"1"。製品版では"0"
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u8: 5;
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u8: 6;
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u8 for_korea:1; // For Korea
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u8 for_china:1; // For China
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u8 rom_version; // Rom version
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u8 comp_arm9_boot_area:1; // Compress arm9 boot area
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u8 comp_arm7_boot_area:1; // Compress arm7 boot area
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u8 inspect_card:1; // Show inspect card
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u8 disable_clear_memory_pad:1; // for Debugger
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u8 enable_twl_rom_cache_read:1; // Enable TWL ROM cacheRead command
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u8: 1;
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u8 warning_no_spec_rom_speed:1;// Warning not to specify rom speed
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u8 disable_detect_pull_out:1; //
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//
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// 0x020 for Static modules (Section:B)
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//
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// ARM9
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u32 main_rom_offset; // ROM offset
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void *main_entry_address; // Entry point
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void *main_ram_address; // RAM address
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u32 main_size; // Module size
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// ARM7
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u32 sub_rom_offset; // ROM offset
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void *sub_entry_address; // Entry point
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void *sub_ram_address; // RAM address
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u32 sub_size; // Module size
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//
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// 0x040 for File Name Table[FNT] (Section:C)
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//
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struct ROM_FNT *fnt_offset; // ROM offset
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u32 fnt_size; // Table size
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//
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// 0x048 for File Allocation Table[FAT] (Section:E)
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//
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struct ROM_FAT *fat_offset; // ROM offset
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u32 fat_size; // Table size
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//
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// 0x050 for Overlay Tables[OVT] (Section:D)
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//
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// ARM9
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struct ROM_OVT *main_ovt_offset; // ROM offset
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u32 main_ovt_size; // Table size
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// ARM7
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struct ROM_OVT *sub_ovt_offset; // ROM offset
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u32 sub_ovt_size; // Table size
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// 0x060 for ROM control parameter (Section:F)
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u32 game_cmd_param; // Game command parameter
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u32 secure_cmd_param; // Secure command parameter
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u32 banner_offset; // Banner ROM offset
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u16 secure_area_crc16; // Secure area CRC-16
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u16 secure_cmd_latency; // Secure command latency ((param+2)*256 system cycles)
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// since NITRO-SDK 2.0PR4
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void *main_autoload_done; // ARM9 autoload done callback address (debug purpose)
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void *sub_autoload_done; // ARM7 autoload done callback address (debug purpose)
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u8 ctrl_reserved_B[8]; // Ctrl Reserved B (Set 0)
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// since NITRO-SDK 2.0PR6
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u32 rom_valid_size; // ROM Original Size
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u32 rom_header_size; // ROM Header size
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u32 main_module_param_offset; // Offset for table of ARM9 module parameters
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u32 sub_module_param_offset; // Offset for table of ARM7 module parameters
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// 0x090 - 0x0C0 System Reserved
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u16 twl_card_normal_area_rom_offset; // undeveloped
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u16 twl_card_keytable_area_rom_offset; // undeveloped
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u16 nand_card_dl_area_rom_offset; // undeveloped
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u16 nand_card_bk_area_rom_offset; // undeveloped
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u8 nand_card_flag; // undeveloped
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u8 reserved_B[39];
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// 0x0C0 for NINTENDO logo data
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u8 nintendo_logo[ NINTENDO_LOGO_DATA_LENGTH ]; // NINTENDO logo data
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u16 nintendo_logo_crc16; // CRC-16
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// 0x15E ROM header CRC-16
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u16 header_crc16; // ROM header CRC-16
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// 0x160 - 0x180 Debugger Reserved
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u8 reserved_C[32]; // Debugger Reserved (Set ALL 0)
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//==========================================================
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//
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// TWL only
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//
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//==========================================================
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// 0x180 - 0x190 TWL-WRAM A/B/C ARM9 configuration data
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u32 main_wram_config_data[8]; // developing...
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// 0x1A0 - 0x1B0 TWL-WRAM A/B/C ARM7 configuration data
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u32 sub_wram_config_data[4]; // developing...
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// 0x1B0 - reserved.
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u8 reserved_ltd_A[ 8 ];
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// 0x1B8 - ARM7-SCFG
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u32 arm7_scfg_ext; // SCFG-EXT
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u8 arm7_scfg_clk; // SCFG-CLK
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// padding(2byte)
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u8 reserved_ltd_A2[ 2 ];
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// 0x1BF - TWL expansion flags
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u8 codec_mode:1; // 0:NTR mode, 1:TWL mode // undeveloped
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u8 otherParentalControls:1; // 1: Enable OtherParentalControls
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u8 saveBannerFile:1; // 1: Enable SaveBannerFile
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u8 wifiConnection:1; // 1: Use WiFiConnection
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u8 rsv:4;
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// 0x1C0 for EX Static modules
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//
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// ARM9
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u32 main_ltd_rom_offset; // ROM offset // undeveloped
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u8 reserved_ltd_B[ 4 ];
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void *main_ltd_ram_address; // RAM address // undeveloped //
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u32 main_ltd_size; // Module size // undeveloped //
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// ARM7
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u32 sub_ltd_rom_offset; // ROM offset // undeveloped
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u8 reserved_ltd_C[ 4 ];
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void *sub_ltd_ram_address; // RAM address // undeveloped //
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u32 sub_ltd_size; // Module size // undeveloped //
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/* 注意： os_reset.c / crt0.HYB.c / crt0.LTD.c 内で 0x01c0 ～ 0x01e0 のアドレスを
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ハードコーディングしています。 これら８つのメンバのオフセットを変更しないで下さい。 */
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// 0x01E0 - 0x01E8 for NITRO digest area offset & size
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u32 nitro_digest_area_rom_offset;
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u32 nitro_digest_area_size;
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// 0x01E8 - 0x01F0 for TWL digest area offset & size
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u32 twl_digest_area_rom_offset;
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u32 twl_digest_area_size;
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// 0x01F0 - 0x01F8 for FS digest table1 offset & size
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u32 digest1_table_offset;
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u32 digest1_table_size;
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// 0x01F8 - 0x0200 for FS digest table1 offset
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u32 digest2_table_offset;
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u32 digest2_table_size;
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// 0x0200 - 0x0208 for FS digest config parameters
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u32 digest1_block_size;
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u32 digest2_covered_digest1_num;
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// 0x0208 - 0x0210 for Banner for TWL
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u32 banner_twl_offset;
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u32 banner_twl_size;
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// 0x0210 - 0x0218 for TWL rom valid size
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u32 twl_rom_valid_size; // ROM Original Size
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u8 reserved_ltd_D[ 4 ];
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// 0x0218 - 0x0220 for TWL ltd module param offset
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u32 main_ltd_module_param_offset; // Offset for table of ARM9 ltd module parameters
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u32 sub_ltd_module_param_offset; // Offset for table of ARM7 ltd module parameters
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// 0x0220 - 0x0230 for AES target offset & size
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u32 aes_target_rom_offset;
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u32 aes_target_size;
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u32 aes_target2_rom_offset; // 予約
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u32 aes_target2_size; // 予約
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// 0x0230 - 0x0238 for TitleID
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union {
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u64 titleID;
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struct {
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u8 titleID_Lo[ 4 ];
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u32 titleID_Hi;
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};
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};
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/* 注意： os_reset.c / crt0.HYB.c / crt0.LTD.c 内で 0x0234 をハードコーディングしています。
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titleID_Hi のオフセットを変更しないで下さい。 */
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// 0x0238 - 0x0240 for Public & Private Save Data Size
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u32 public_save_data_size;
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u32 private_save_data_size;
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// 0x0240 - 0x02f0 reserved.
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u8 reserved_ltd_F[ 0x2f0 - 0x240 ];
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// 0x02f0 - 0x0300 Parental Controls Rating Info
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u8 ParentalControlsRatingInfo[ 0x10 ];
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// 0x0300 - 0x0378 Rom Segment Digest
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u8 main_static_digest[ DIGEST_SIZE_SHA1 ];
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u8 sub_static_digest[ DIGEST_SIZE_SHA1 ];
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u8 digest2_table_digest[ DIGEST_SIZE_SHA1 ];
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u8 banner_twl_digest[ DIGEST_SIZE_SHA1 ];
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u8 main_ltd_static_digest[ DIGEST_SIZE_SHA1 ];
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u8 sub_ltd_static_digest[ DIGEST_SIZE_SHA1 ];
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}
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ROM_Header_Short;
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typedef struct
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{
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struct ROM_Header_Short s;
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////
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//// EXTRA SYSTEM REGION
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////
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//
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// 0x02f0 - 0x0e00 System Reserved
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//
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u8 reserved_D[4 * 1024 - sizeof(ROM_Header_Short) - sizeof(RomCertificate) - RSA_KEY_LENGTH ]; // Reserved D
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//
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// 0x0e00 - 0x0f80 ROM Certificate
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//
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RomCertificate certificate;
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//
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// 0x0f80 - 0x1000 ROM Header Signature
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//
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u8 signature[ RSA_KEY_LENGTH ]; // PKCS#1_v1.5の形式でフォーマットされたSignatureDataが、RSA暗号化された状態
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//
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// 0x01000 - 0x04000 System Reserved
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//
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u8 reserved_E[12 * 1024]; // Reserved E
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}
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ROM_Header; // 16KB
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#endif
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