From ff2133e112d8b3a9cb9de77a89ca09539a1b385e Mon Sep 17 00:00:00 2001 From: yutaka Date: Mon, 28 Jul 2008 00:50:09 +0000 Subject: [PATCH] =?UTF-8?q?WRAM=E3=81=AE=E5=88=9D=E6=9C=9F=E5=80=A4?= =?UTF-8?q?=E3=82=92=E7=B5=B1=E4=B8=80?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit git-svn-id: file:///Users/lillianskinner/Downloads/platinum/twl/TwlIPL/trunk@2005 b08762b0-b915-fc4b-9d8c-17b2551a87ff --- .../gcdfirm-disp/wram_regs/wram_regs.c | 15 +++- .../wram_regs/wram_regs.c | 11 ++- .../sdmc-launcher/wram_regs/wram_regs.c | 11 ++- .../sdmc-launcher/wram_regs/wram_regs.c | 9 +- build/norfirm/firm-dev/wram_regs/wram_regs.c | 11 ++- .../norfirm-print/wram_regs/wram_regs.c | 89 ++++++++++--------- 6 files changed, 94 insertions(+), 52 deletions(-) diff --git a/build/gcdfirm/gcdfirm-disp/wram_regs/wram_regs.c b/build/gcdfirm/gcdfirm-disp/wram_regs/wram_regs.c index f03e0e14..7652aac6 100644 --- a/build/gcdfirm/gcdfirm-disp/wram_regs/wram_regs.c +++ b/build/gcdfirm/gcdfirm-disp/wram_regs/wram_regs.c @@ -1,5 +1,5 @@ /*---------------------------------------------------------------------------* - Project: TwlFirm - tools - nandfirm + Project: TwlFirm - tools - gcdfirm File: wram_regs.c Copyright 2007 Nintendo. All rights reserved. @@ -10,8 +10,8 @@ not be disclosed to third parties or copied or duplicated in any form, in whole or in part, without the prior written consent of Nintendo. - $Date:: 2007-11-12#$ - $Rev: 149 $ + $Date:: 2008-07-25#$ + $Rev: 1994 $ $Author: yutaka $ *---------------------------------------------------------------------------*/ #include @@ -34,7 +34,8 @@ MIHeader_WramRegs wram_regs_init = REG_MI_MBK_B4_FIELD( 1, MI_WRAM_BC_OFFSET_128KB, MI_WRAM_ARM7 ), REG_MI_MBK_B5_FIELD( 1, MI_WRAM_BC_OFFSET_160KB, MI_WRAM_ARM7 ), REG_MI_MBK_B6_FIELD( 1, MI_WRAM_BC_OFFSET_192KB, MI_WRAM_ARM7 ), - REG_MI_MBK_B7_FIELD( 1, MI_WRAM_BC_OFFSET_224KB, MI_WRAM_ARM7 ), +// REG_MI_MBK_B7_FIELD( 1, MI_WRAM_BC_OFFSET_224KB, MI_WRAM_ARM7 ), + REG_MI_MBK_B7_FIELD( 1, MI_WRAM_BC_OFFSET_224KB, MI_WRAM_ARM9 ), }, { REG_MI_MBK_C0_FIELD( 1, MI_WRAM_BC_OFFSET_0KB , MI_WRAM_ARM7 ), @@ -50,10 +51,16 @@ MIHeader_WramRegs wram_regs_init = MI_WRAM_IMAGE_256KB, REG_WRAM_MAP_CONV_ADDR( 6, A, SADDR, HW_WRAM_AREA_HALF - HW_WRAM_A_SIZE ) ), +/* REG_MI_MBK7_FIELD( REG_WRAM_MAP_CONV_ADDR( 7, B, EADDR, HW_WRAM_AREA + HW_WRAM_B_SIZE ), MI_WRAM_IMAGE_256KB, REG_WRAM_MAP_CONV_ADDR( 7, B, SADDR, HW_WRAM_AREA ) ), +*/ + REG_MI_MBK7_FIELD( REG_WRAM_MAP_CONV_ADDR( 7, B, EADDR, HW_WRAM_AREA_HALF - HW_WRAM_A_SIZE ), // joint to WRAM-A + MI_WRAM_IMAGE_256KB, + REG_WRAM_MAP_CONV_ADDR( 7, B, SADDR, HW_WRAM_AREA ) + ), REG_MI_MBK8_FIELD( REG_WRAM_MAP_CONV_ADDR( 8, C, EADDR, MI_WRAM_MAP_NULL ), MI_WRAM_IMAGE_256KB, REG_WRAM_MAP_CONV_ADDR( 8, C, SADDR, MI_WRAM_MAP_NULL ) diff --git a/build/gcdfirm/sdmc-launcher-writer/wram_regs/wram_regs.c b/build/gcdfirm/sdmc-launcher-writer/wram_regs/wram_regs.c index 2454b302..aaa4dc33 100644 --- a/build/gcdfirm/sdmc-launcher-writer/wram_regs/wram_regs.c +++ b/build/gcdfirm/sdmc-launcher-writer/wram_regs/wram_regs.c @@ -1,5 +1,5 @@ /*---------------------------------------------------------------------------* - Project: TwlFirm - tools - nandfirm + Project: TwlFirm - tools - gcdfirm File: wram_regs.c Copyright 2007 Nintendo. All rights reserved. @@ -34,7 +34,8 @@ MIHeader_WramRegs wram_regs_init = REG_MI_MBK_B4_FIELD( 1, MI_WRAM_BC_OFFSET_128KB, MI_WRAM_ARM7 ), REG_MI_MBK_B5_FIELD( 1, MI_WRAM_BC_OFFSET_160KB, MI_WRAM_ARM7 ), REG_MI_MBK_B6_FIELD( 1, MI_WRAM_BC_OFFSET_192KB, MI_WRAM_ARM7 ), - REG_MI_MBK_B7_FIELD( 1, MI_WRAM_BC_OFFSET_224KB, MI_WRAM_ARM7 ), +// REG_MI_MBK_B7_FIELD( 1, MI_WRAM_BC_OFFSET_224KB, MI_WRAM_ARM7 ), + REG_MI_MBK_B7_FIELD( 1, MI_WRAM_BC_OFFSET_224KB, MI_WRAM_ARM9 ), }, { REG_MI_MBK_C0_FIELD( 1, MI_WRAM_BC_OFFSET_0KB , MI_WRAM_ARM7 ), @@ -50,10 +51,16 @@ MIHeader_WramRegs wram_regs_init = MI_WRAM_IMAGE_256KB, REG_WRAM_MAP_CONV_ADDR( 6, A, SADDR, HW_WRAM_AREA_HALF - HW_WRAM_A_SIZE ) ), +/* REG_MI_MBK7_FIELD( REG_WRAM_MAP_CONV_ADDR( 7, B, EADDR, HW_WRAM_AREA + HW_WRAM_B_SIZE ), MI_WRAM_IMAGE_256KB, REG_WRAM_MAP_CONV_ADDR( 7, B, SADDR, HW_WRAM_AREA ) ), +*/ + REG_MI_MBK7_FIELD( REG_WRAM_MAP_CONV_ADDR( 7, B, EADDR, HW_WRAM_AREA_HALF - HW_WRAM_A_SIZE ), // joint to WRAM-A + MI_WRAM_IMAGE_256KB, + REG_WRAM_MAP_CONV_ADDR( 7, B, SADDR, HW_WRAM_AREA ) + ), REG_MI_MBK8_FIELD( REG_WRAM_MAP_CONV_ADDR( 8, C, EADDR, MI_WRAM_MAP_NULL ), MI_WRAM_IMAGE_256KB, REG_WRAM_MAP_CONV_ADDR( 8, C, SADDR, MI_WRAM_MAP_NULL ) diff --git a/build/gcdfirm/sdmc-launcher/wram_regs/wram_regs.c b/build/gcdfirm/sdmc-launcher/wram_regs/wram_regs.c index 2454b302..aaa4dc33 100644 --- a/build/gcdfirm/sdmc-launcher/wram_regs/wram_regs.c +++ b/build/gcdfirm/sdmc-launcher/wram_regs/wram_regs.c @@ -1,5 +1,5 @@ /*---------------------------------------------------------------------------* - Project: TwlFirm - tools - nandfirm + Project: TwlFirm - tools - gcdfirm File: wram_regs.c Copyright 2007 Nintendo. All rights reserved. @@ -34,7 +34,8 @@ MIHeader_WramRegs wram_regs_init = REG_MI_MBK_B4_FIELD( 1, MI_WRAM_BC_OFFSET_128KB, MI_WRAM_ARM7 ), REG_MI_MBK_B5_FIELD( 1, MI_WRAM_BC_OFFSET_160KB, MI_WRAM_ARM7 ), REG_MI_MBK_B6_FIELD( 1, MI_WRAM_BC_OFFSET_192KB, MI_WRAM_ARM7 ), - REG_MI_MBK_B7_FIELD( 1, MI_WRAM_BC_OFFSET_224KB, MI_WRAM_ARM7 ), +// REG_MI_MBK_B7_FIELD( 1, MI_WRAM_BC_OFFSET_224KB, MI_WRAM_ARM7 ), + REG_MI_MBK_B7_FIELD( 1, MI_WRAM_BC_OFFSET_224KB, MI_WRAM_ARM9 ), }, { REG_MI_MBK_C0_FIELD( 1, MI_WRAM_BC_OFFSET_0KB , MI_WRAM_ARM7 ), @@ -50,10 +51,16 @@ MIHeader_WramRegs wram_regs_init = MI_WRAM_IMAGE_256KB, REG_WRAM_MAP_CONV_ADDR( 6, A, SADDR, HW_WRAM_AREA_HALF - HW_WRAM_A_SIZE ) ), +/* REG_MI_MBK7_FIELD( REG_WRAM_MAP_CONV_ADDR( 7, B, EADDR, HW_WRAM_AREA + HW_WRAM_B_SIZE ), MI_WRAM_IMAGE_256KB, REG_WRAM_MAP_CONV_ADDR( 7, B, SADDR, HW_WRAM_AREA ) ), +*/ + REG_MI_MBK7_FIELD( REG_WRAM_MAP_CONV_ADDR( 7, B, EADDR, HW_WRAM_AREA_HALF - HW_WRAM_A_SIZE ), // joint to WRAM-A + MI_WRAM_IMAGE_256KB, + REG_WRAM_MAP_CONV_ADDR( 7, B, SADDR, HW_WRAM_AREA ) + ), REG_MI_MBK8_FIELD( REG_WRAM_MAP_CONV_ADDR( 8, C, EADDR, MI_WRAM_MAP_NULL ), MI_WRAM_IMAGE_256KB, REG_WRAM_MAP_CONV_ADDR( 8, C, SADDR, MI_WRAM_MAP_NULL ) diff --git a/build/nandfirm/sdmc-launcher/wram_regs/wram_regs.c b/build/nandfirm/sdmc-launcher/wram_regs/wram_regs.c index 2454b302..7e727571 100644 --- a/build/nandfirm/sdmc-launcher/wram_regs/wram_regs.c +++ b/build/nandfirm/sdmc-launcher/wram_regs/wram_regs.c @@ -34,7 +34,8 @@ MIHeader_WramRegs wram_regs_init = REG_MI_MBK_B4_FIELD( 1, MI_WRAM_BC_OFFSET_128KB, MI_WRAM_ARM7 ), REG_MI_MBK_B5_FIELD( 1, MI_WRAM_BC_OFFSET_160KB, MI_WRAM_ARM7 ), REG_MI_MBK_B6_FIELD( 1, MI_WRAM_BC_OFFSET_192KB, MI_WRAM_ARM7 ), - REG_MI_MBK_B7_FIELD( 1, MI_WRAM_BC_OFFSET_224KB, MI_WRAM_ARM7 ), +// REG_MI_MBK_B7_FIELD( 1, MI_WRAM_BC_OFFSET_224KB, MI_WRAM_ARM7 ), + REG_MI_MBK_B7_FIELD( 1, MI_WRAM_BC_OFFSET_224KB, MI_WRAM_ARM9 ), }, { REG_MI_MBK_C0_FIELD( 1, MI_WRAM_BC_OFFSET_0KB , MI_WRAM_ARM7 ), @@ -50,10 +51,16 @@ MIHeader_WramRegs wram_regs_init = MI_WRAM_IMAGE_256KB, REG_WRAM_MAP_CONV_ADDR( 6, A, SADDR, HW_WRAM_AREA_HALF - HW_WRAM_A_SIZE ) ), +/* REG_MI_MBK7_FIELD( REG_WRAM_MAP_CONV_ADDR( 7, B, EADDR, HW_WRAM_AREA + HW_WRAM_B_SIZE ), MI_WRAM_IMAGE_256KB, REG_WRAM_MAP_CONV_ADDR( 7, B, SADDR, HW_WRAM_AREA ) ), +*/ + REG_MI_MBK7_FIELD( REG_WRAM_MAP_CONV_ADDR( 7, B, EADDR, HW_WRAM_AREA_HALF - HW_WRAM_A_SIZE ), // joint to WRAM-A + MI_WRAM_IMAGE_256KB, + REG_WRAM_MAP_CONV_ADDR( 7, B, SADDR, HW_WRAM_AREA ) + ), REG_MI_MBK8_FIELD( REG_WRAM_MAP_CONV_ADDR( 8, C, EADDR, MI_WRAM_MAP_NULL ), MI_WRAM_IMAGE_256KB, REG_WRAM_MAP_CONV_ADDR( 8, C, SADDR, MI_WRAM_MAP_NULL ) diff --git a/build/norfirm/firm-dev/wram_regs/wram_regs.c b/build/norfirm/firm-dev/wram_regs/wram_regs.c index 2454b302..4d052220 100644 --- a/build/norfirm/firm-dev/wram_regs/wram_regs.c +++ b/build/norfirm/firm-dev/wram_regs/wram_regs.c @@ -1,5 +1,5 @@ /*---------------------------------------------------------------------------* - Project: TwlFirm - tools - nandfirm + Project: TwlFirm - tools - norfirm File: wram_regs.c Copyright 2007 Nintendo. All rights reserved. @@ -34,7 +34,8 @@ MIHeader_WramRegs wram_regs_init = REG_MI_MBK_B4_FIELD( 1, MI_WRAM_BC_OFFSET_128KB, MI_WRAM_ARM7 ), REG_MI_MBK_B5_FIELD( 1, MI_WRAM_BC_OFFSET_160KB, MI_WRAM_ARM7 ), REG_MI_MBK_B6_FIELD( 1, MI_WRAM_BC_OFFSET_192KB, MI_WRAM_ARM7 ), - REG_MI_MBK_B7_FIELD( 1, MI_WRAM_BC_OFFSET_224KB, MI_WRAM_ARM7 ), +// REG_MI_MBK_B7_FIELD( 1, MI_WRAM_BC_OFFSET_224KB, MI_WRAM_ARM7 ), + REG_MI_MBK_B7_FIELD( 1, MI_WRAM_BC_OFFSET_224KB, MI_WRAM_ARM9 ), }, { REG_MI_MBK_C0_FIELD( 1, MI_WRAM_BC_OFFSET_0KB , MI_WRAM_ARM7 ), @@ -50,10 +51,16 @@ MIHeader_WramRegs wram_regs_init = MI_WRAM_IMAGE_256KB, REG_WRAM_MAP_CONV_ADDR( 6, A, SADDR, HW_WRAM_AREA_HALF - HW_WRAM_A_SIZE ) ), +/* REG_MI_MBK7_FIELD( REG_WRAM_MAP_CONV_ADDR( 7, B, EADDR, HW_WRAM_AREA + HW_WRAM_B_SIZE ), MI_WRAM_IMAGE_256KB, REG_WRAM_MAP_CONV_ADDR( 7, B, SADDR, HW_WRAM_AREA ) ), +*/ + REG_MI_MBK7_FIELD( REG_WRAM_MAP_CONV_ADDR( 7, B, EADDR, HW_WRAM_AREA_HALF - HW_WRAM_A_SIZE ), // joint to WRAM-A + MI_WRAM_IMAGE_256KB, + REG_WRAM_MAP_CONV_ADDR( 7, B, SADDR, HW_WRAM_AREA ) + ), REG_MI_MBK8_FIELD( REG_WRAM_MAP_CONV_ADDR( 8, C, EADDR, MI_WRAM_MAP_NULL ), MI_WRAM_IMAGE_256KB, REG_WRAM_MAP_CONV_ADDR( 8, C, SADDR, MI_WRAM_MAP_NULL ) diff --git a/build/norfirm/norfirm-print/wram_regs/wram_regs.c b/build/norfirm/norfirm-print/wram_regs/wram_regs.c index ea59c659..4d052220 100644 --- a/build/norfirm/norfirm-print/wram_regs/wram_regs.c +++ b/build/norfirm/norfirm-print/wram_regs/wram_regs.c @@ -1,5 +1,5 @@ /*---------------------------------------------------------------------------* - Project: TwlFirm - tools - makenorfirm + Project: TwlFirm - tools - norfirm File: wram_regs.c Copyright 2007 Nintendo. All rights reserved. @@ -11,8 +11,8 @@ in whole or in part, without the prior written consent of Nintendo. $Date:: $ - $Rev:$ - $Author:$ + $Rev$ + $Author$ *---------------------------------------------------------------------------*/ #include #include @@ -21,10 +21,10 @@ MIHeader_WramRegs wram_regs_init = { // ARM9 { - REG_MI_MBK_A0_FIELD( 1, MI_WRAM_A_OFFSET_0KB , MI_WRAM_ARM7 ), - REG_MI_MBK_A1_FIELD( 1, MI_WRAM_A_OFFSET_64KB , MI_WRAM_ARM7 ), - REG_MI_MBK_A2_FIELD( 1, MI_WRAM_A_OFFSET_128KB, MI_WRAM_ARM7 ), - REG_MI_MBK_A3_FIELD( 1, MI_WRAM_A_OFFSET_192KB, MI_WRAM_ARM7 ), + REG_MI_MBK_A0_FIELD( 1, MI_WRAM_A_OFFSET_0KB , MI_WRAM_ARM9 ), + REG_MI_MBK_A1_FIELD( 1, MI_WRAM_A_OFFSET_64KB , MI_WRAM_ARM9 ), + REG_MI_MBK_A2_FIELD( 1, MI_WRAM_A_OFFSET_128KB, MI_WRAM_ARM9 ), + REG_MI_MBK_A3_FIELD( 1, MI_WRAM_A_OFFSET_192KB, MI_WRAM_ARM9 ), }, { REG_MI_MBK_B0_FIELD( 1, MI_WRAM_BC_OFFSET_0KB , MI_WRAM_ARM7 ), @@ -34,46 +34,53 @@ MIHeader_WramRegs wram_regs_init = REG_MI_MBK_B4_FIELD( 1, MI_WRAM_BC_OFFSET_128KB, MI_WRAM_ARM7 ), REG_MI_MBK_B5_FIELD( 1, MI_WRAM_BC_OFFSET_160KB, MI_WRAM_ARM7 ), REG_MI_MBK_B6_FIELD( 1, MI_WRAM_BC_OFFSET_192KB, MI_WRAM_ARM7 ), - REG_MI_MBK_B7_FIELD( 1, MI_WRAM_BC_OFFSET_224KB, MI_WRAM_ARM7 ), +// REG_MI_MBK_B7_FIELD( 1, MI_WRAM_BC_OFFSET_224KB, MI_WRAM_ARM7 ), + REG_MI_MBK_B7_FIELD( 1, MI_WRAM_BC_OFFSET_224KB, MI_WRAM_ARM9 ), }, { - REG_MI_MBK_C0_FIELD( 1, MI_WRAM_BC_OFFSET_0KB , MI_WRAM_ARM9 ), - REG_MI_MBK_C1_FIELD( 1, MI_WRAM_BC_OFFSET_32KB , MI_WRAM_ARM9 ), - REG_MI_MBK_C2_FIELD( 1, MI_WRAM_BC_OFFSET_64KB , MI_WRAM_ARM9 ), - REG_MI_MBK_C3_FIELD( 1, MI_WRAM_BC_OFFSET_96KB , MI_WRAM_ARM9 ), - REG_MI_MBK_C4_FIELD( 1, MI_WRAM_BC_OFFSET_128KB, MI_WRAM_ARM9 ), - REG_MI_MBK_C5_FIELD( 1, MI_WRAM_BC_OFFSET_160KB, MI_WRAM_ARM9 ), - REG_MI_MBK_C6_FIELD( 1, MI_WRAM_BC_OFFSET_192KB, MI_WRAM_ARM9 ), - REG_MI_MBK_C7_FIELD( 1, MI_WRAM_BC_OFFSET_224KB, MI_WRAM_ARM9 ), + REG_MI_MBK_C0_FIELD( 1, MI_WRAM_BC_OFFSET_0KB , MI_WRAM_ARM7 ), + REG_MI_MBK_C1_FIELD( 1, MI_WRAM_BC_OFFSET_32KB , MI_WRAM_ARM7 ), + REG_MI_MBK_C2_FIELD( 1, MI_WRAM_BC_OFFSET_64KB , MI_WRAM_ARM7 ), + REG_MI_MBK_C3_FIELD( 1, MI_WRAM_BC_OFFSET_96KB , MI_WRAM_ARM7 ), + REG_MI_MBK_C4_FIELD( 1, MI_WRAM_BC_OFFSET_128KB, MI_WRAM_ARM7 ), + REG_MI_MBK_C5_FIELD( 1, MI_WRAM_BC_OFFSET_160KB, MI_WRAM_ARM7 ), + REG_MI_MBK_C6_FIELD( 1, MI_WRAM_BC_OFFSET_192KB, MI_WRAM_ARM7 ), + REG_MI_MBK_C7_FIELD( 1, MI_WRAM_BC_OFFSET_224KB, MI_WRAM_ARM7 ), }, - REG_MI_MBK6_FIELD( REG_WRAM_MAP_CONV_ADDR( 6, A, EADDR, MI_WRAM_MAP_NULL ), - MI_WRAM_IMAGE_128KB, - REG_WRAM_MAP_CONV_ADDR( 6, A, SADDR, MI_WRAM_MAP_NULL ) - ), - REG_MI_MBK7_FIELD( REG_WRAM_MAP_CONV_ADDR( 7, B, EADDR, MI_WRAM_MAP_NULL ), - MI_WRAM_IMAGE_128KB, - REG_WRAM_MAP_CONV_ADDR( 7, B, SADDR, MI_WRAM_MAP_NULL ) - ), - REG_MI_MBK8_FIELD( REG_WRAM_MAP_CONV_ADDR( 8, C, EADDR, HW_WRAM_AREA_HALF + 0x00020000 ), - MI_WRAM_IMAGE_128KB, - REG_WRAM_MAP_CONV_ADDR( 8, C, SADDR, HW_WRAM_AREA_HALF ) - ), + REG_MI_MBK6_FIELD( REG_WRAM_MAP_CONV_ADDR( 6, A, EADDR, HW_WRAM_AREA_HALF ), + MI_WRAM_IMAGE_256KB, + REG_WRAM_MAP_CONV_ADDR( 6, A, SADDR, HW_WRAM_AREA_HALF - HW_WRAM_A_SIZE ) + ), +/* + REG_MI_MBK7_FIELD( REG_WRAM_MAP_CONV_ADDR( 7, B, EADDR, HW_WRAM_AREA + HW_WRAM_B_SIZE ), + MI_WRAM_IMAGE_256KB, + REG_WRAM_MAP_CONV_ADDR( 7, B, SADDR, HW_WRAM_AREA ) + ), +*/ + REG_MI_MBK7_FIELD( REG_WRAM_MAP_CONV_ADDR( 7, B, EADDR, HW_WRAM_AREA_HALF - HW_WRAM_A_SIZE ), // joint to WRAM-A + MI_WRAM_IMAGE_256KB, + REG_WRAM_MAP_CONV_ADDR( 7, B, SADDR, HW_WRAM_AREA ) + ), + REG_MI_MBK8_FIELD( REG_WRAM_MAP_CONV_ADDR( 8, C, EADDR, MI_WRAM_MAP_NULL ), + MI_WRAM_IMAGE_256KB, + REG_WRAM_MAP_CONV_ADDR( 8, C, SADDR, MI_WRAM_MAP_NULL ) + ), // ARM7 - REG_MI_MBK6_FIELD( REG_WRAM_MAP_CONV_ADDR( 6, A, EADDR, HW_WRAM_AREA_HALF + 0x00020000 ), - MI_WRAM_IMAGE_128KB, - REG_WRAM_MAP_CONV_ADDR( 6, A, SADDR, HW_WRAM_AREA_HALF ) - ), - REG_MI_MBK7_FIELD( REG_WRAM_MAP_CONV_ADDR( 7, B, EADDR, HW_WRAM_AREA_HALF + 0x00040000 ), - MI_WRAM_IMAGE_128KB, - REG_WRAM_MAP_CONV_ADDR( 7, B, SADDR, HW_WRAM_AREA_HALF + 0x00020000 ) - ), - REG_MI_MBK8_FIELD( REG_WRAM_MAP_CONV_ADDR( 8, C, EADDR, MI_WRAM_MAP_NULL ), - MI_WRAM_IMAGE_128KB, - REG_WRAM_MAP_CONV_ADDR( 8, C, SADDR, MI_WRAM_MAP_NULL ) - ), + REG_MI_MBK6_FIELD( REG_WRAM_MAP_CONV_ADDR( 6, A, EADDR, MI_WRAM_MAP_NULL ), + MI_WRAM_IMAGE_256KB, + REG_WRAM_MAP_CONV_ADDR( 6, A, SADDR, MI_WRAM_MAP_NULL ) + ), + REG_MI_MBK7_FIELD( REG_WRAM_MAP_CONV_ADDR( 7, B, EADDR, HW_WRAM_AREA + HW_WRAM_B_SIZE ), + MI_WRAM_IMAGE_256KB, + REG_WRAM_MAP_CONV_ADDR( 7, B, SADDR, HW_WRAM_AREA ) + ), + REG_MI_MBK8_FIELD( REG_WRAM_MAP_CONV_ADDR( 8, C, EADDR, HW_WRAM_AREA_HALF - HW_WRAM_SIZE ), + MI_WRAM_IMAGE_256KB, + REG_WRAM_MAP_CONV_ADDR( 8, C, SADDR, HW_WRAM_AREA_HALF - HW_WRAM_SIZE - HW_WRAM_C_SIZE ) + ), - // WRAM Lock + // WRAM Lock { 0, 0,