MIi_InitMainMemCRの修正

MIi_GetMainMemCRの追加

git-svn-id: file:///Users/lillianskinner/Downloads/platinum/twl/TwlIPL/trunk@49 b08762b0-b915-fc4b-9d8c-17b2551a87ff

build/libraries/init/ARM9/crt0_firm.c

@@ -98,7 +98,9 @@ SDK_WEAK_SYMBOL asm void _start( void )
 
         //---- initialize Main Memory
         cmp             r0, #FIRM_PXI_ID_COLDBOOT
-        bleq            MIi_InitMainMemCR
+        moveq           r0, #TRUE
+        movne           r0, #FALSE
+        bl              MIi_InitMainMemCR
 
         mov             r0, #FIRM_PXI_ID_INIT_MMEM
         bl              PXI_SendByIntf

build/libraries/mi/ARM9/mi_init_mainMemory.c

@@ -16,6 +16,7 @@
  *---------------------------------------------------------------------------*/
 #include        <firm/mi.h>
 
+void MIi_InitMainMemCRCore( void );
 
 /*---------------------------------------------------------------------------*
   Name:         MIi_IsMainMemoryInitialized
@@ -59,52 +60,39 @@ void MIi_WaitMainMemoryInitialize( void )
  *---------------------------------------------------------------------------*/
 #include        <nitro/code32.h>
 
-asm void  MIi_InitMainMemCR( void )
+asm void  MIi_InitMainMemCR( BOOL setCR )
 {
         mov     r12, lr
 
-        mov     r0, #0x10000        // low period 0.97ms
+        mov     r2, r0
+
+        mov     r0, #0x8000        // low period 0.97ms
         bl      OS_SpinWaitCpuCycles
 
         ldr     r3, =REG_EXMEMCNT_ADDR
         mov     r1, #REG_MI_EXMEMCNT_CE2_MASK
-        ldrh    r2, [r3]
+        ldrh    r0, [r3]
-        tst     r2, r1
+        tst     r0, r1
         bxne    r12
 
         strh    r1, [r3]
 
-        mov     r0, #0x10000        // high period 0.97ms
+        mov     r0, #0x8000        // high period 0.97ms
         bl      OS_SpinWaitCpuCycles
 
-        ldr     r3,  =HW_WRAM_AREA - 2
+        cmp     r2, #FALSE
-#ifdef SDK_BB
+        beq     @10
-        ldr     r0,  =MMEM_DCR0_BURST_MODE | MMEM_DCR0_BURST_CONTINUOUS \
-                    | MMEM_DCR0_PARTIAL_REFRESH_NONE | MMEM_DCR0_SB1
-        ldr     r1,  =MMEM_DCR1_1ST_R4_W3  | MMEM_DCR1_BURST_WRITE | MMEM_DCR1_BURST_LINER \
-                    | MMEM_DCR1_CLOCK_TRIGGER_UP | MMEM_DCR1_SB1
-        ldr     r2, =HW_MAIN_MEM | MMEM_DCR2_CLOCK_TRIGGER_UP \
-                    | MMEM_DCR2_BURST_MODE | MMEM_DCR2_BURST_CONTINUOUS \
-                    | MMEM_DCR2_1ST_R4_W3  | MMEM_DCR2_BURST_WRITE | MMEM_DCR2_BURST_LINER \
-                    | MMEM_DCR2_PARTIAL_REFRESH_NONE | MMEM_DCR2_SB1
-        ldrh    lr, [r3]
-        strh    lr, [r3]
-        strh    lr, [r3]
-        strh    r0, [r3]
-        strh    r1, [r3]
-        ldrh    lr, [r2]
-#else // SDK_BB
-        ldr     r0,  =MMEM_TCR0
-        ldr     r1,  =MMEM_TCR1
-        ldr     r2,  =MMEM_TCR2
-        ldrh    lr, [r3]
-        strh    lr, [r3]
-        strh    lr, [r3]
-        strh    r0, [r3]
-        strh    r1, [r3]
-        strh    r2, [r3]
-#endif // SDK_BB
 
+        // メインメモリが同期モード時（ハードリセット時）に
+        // 非同期モード（CLK固定）でコマンド発行しても大丈夫
+        ldr     r3,  =HW_WRAM_AREA - 2
+        bl      MIi_InitMainMemCRCore
+#ifdef TWL_PLATFORM_TS
+        ldr     r3,  =HW_MAIN_MEM_HI_EX_END - 2
+        bl      MIi_InitMainMemCRCore
+#endif // TWL_PLATFORM_TS
+
+@10:
         ldr     r3, =REG_EXMEMCNT_ADDR
         mov     r1, #REG_MI_EXMEMCNT_IFM_MASK | REG_MI_EXMEMCNT_CE2_MASK
         strh    r1, [r3]
@@ -112,3 +100,61 @@ asm void  MIi_InitMainMemCR( void )
         bx      r12
 }
 
+asm void MIi_InitMainMemCRCore( void )
+{
+//        stmfd   sp!, { lr }
+
+#ifdef TWL_PLATFORM_BB
+        mov     r2, lr
+        ldr     r0,  =MMEM_DCR0_BURST_MODE | MMEM_DCR0_BURST_CONTINUOUS \
+                    | MMEM_DCR0_PARTIAL_REFRESH_NONE | MMEM_DCR0_SB1
+        ldr     r1,  =MMEM_DCR1_1ST_R4_W3  | MMEM_DCR1_BURST_WRITE | MMEM_DCR1_BURST_LINER \
+                    | MMEM_DCR1_CLOCK_TRIGGER_UP | MMEM_DCR1_SB1
+        ldrh    lr, [r3]
+        strh    lr, [r3]
+        strh    lr, [r3]
+        mov     lr, r2
+        ldr     r2, =HW_MAIN_MEM | MMEM_DCR2_CLOCK_TRIGGER_UP \
+                    | MMEM_DCR2_BURST_MODE | MMEM_DCR2_BURST_CONTINUOUS \
+                    | MMEM_DCR2_1ST_R4_W3  | MMEM_DCR2_BURST_WRITE | MMEM_DCR2_BURST_LINER \
+                    | MMEM_DCR2_PARTIAL_REFRESH_NONE | MMEM_DCR2_SB1
+        strh    r0, [r3]
+        strh    r1, [r3]
+        ldrh    r3, [r2]
+#else // TWL_PLATFORM_TS
+        mov     r2, lr
+        ldr     r0,  =MMEM_TCR0
+        ldr     r1,  =MMEM_TCR1
+        ldrh    lr, [r3]
+        strh    lr, [r3]
+        strh    lr, [r3]
+        mov     lr, r2
+        ldr     r2,  =MMEM_TCR2
+        strh    r0, [r3]
+        strh    r1, [r3]
+        strh    r2, [r3]
+#endif // TWL_PLATFORM_TS
+
+//        ldmfd   sp!, { lr }
+        bx      lr
+}
+
+asm void MIi_GetMainMemCR( MIMmemCR* dest )
+{
+#ifdef TWL_PLATFORM_TS
+        ldr     r3,  =HW_WRAM_AREA - 2
+        ldr     r1,  =MMEM_TCR0_R
+        ldrh    r2, [r3]
+        strh    r2, [r3]
+        strh    r2, [r3]
+        strh    r1, [r3]
+        ldrh    r1, [r3]
+        ldrh    r2, [r3]
+        strh    r2, [r0, #4]
+        strh    r1, [r0, #2]
+        ldr     r1,  =MMEM_TCR0_R
+        strh    r1, [r0, #0]
+#endif // TWL_PLATFORM_TS
+
+        bx      lr
+}

include/firm/mi/mainMemory.h

@@ -22,6 +22,14 @@
 extern "C" {
 #endif
 
+typedef struct
+{
+    u16 cr0;
+    u16 cr1;
+    u16 cr2;
+}
+MIMmemCR;
+
 //----------------------------------------------------------------------
 //                      メインメモリ CRコマンド
 //----------------------------------------------------------------------
@@ -69,7 +77,9 @@ extern "C" {
 
   Returns:      None
  *---------------------------------------------------------------------------*/
-void  MIi_InitMainMemCR( void );
+void  MIi_InitMainMemCR( BOOL setCR );
+
+void MIi_GetMainMemCR( MIMmemCR* dest );
 
 /*---------------------------------------------------------------------------*
   Name:         MIi_IsMainMemoryInitialized