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メインメモリ初期化周りをいろいろ修正。

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git-svn-id: file:///Users/lillianskinner/Downloads/platinum/twl/TwlIPL/trunk@205 b08762b0-b915-fc4b-9d8c-17b2551a87ff
This commit is contained in:
yutaka 2007-11-16 11:53:24 +00:00
parent f30feddbf5
commit ad04364b9b
4 changed files with 52 additions and 18 deletions
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11
build/libraries/init/ARM7/crt0_firm.c
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@ -113,7 +113,8 @@ SDK_WEAK_SYMBOL asm void _start( void )
sub sp, r1, #4 // 4byte for stack check code
//---- read reset flag from pmic
#ifdef TWL_PLATFORM_TS
#ifdef FIRM_DISABLE_CR_AT_WARMBOOT
#ifdef SDK_TS
#if 0
mov r0, #REG_PMIC_SW_FLAGS_ADDR
bl PMi_GetRegister
@ -122,15 +123,17 @@ SDK_WEAK_SYMBOL asm void _start( void )
mov r0, #I2C_SLAVE_MICRO_CONTROLLER
mov r1, #MCU_REG_TEMP_ADDR
bl I2Ci_ReadRegister
//ands r0, r0, #0x01 // under construction
cmp r0, #0 // under construction
ldr r2, =HW_RESET_PARAMETER_BUF
str r0, [r2] // store 4 bytes
cmp r0, #0
#endif
movne r0, #FIRM_PXI_ID_WARMBOOT
moveq r0, #FIRM_PXI_ID_COLDBOOT
bl PXI_SendByIntf
mov r0, #FIRM_PXI_ID_INIT_MMEM
bl PXI_WaitByIntf
#endif // TWL_PLATFORM_TS
#endif // SDK_TS
#endif // FIRM_DISABLE_CR_AT_WARMBOOT
//---- wait for main memory mode into burst mode
ldr r3, =REG_EXMEMCNT_L_ADDR

9
build/libraries/init/ARM9/crt0_firm.c
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@ -122,7 +122,8 @@ SDK_WEAK_SYMBOL asm void _start( void )
sub sp, r1, #4 // 4byte for stack check code
//---- read reset flag from pmic
#ifdef TWL_PLATFORM_TS
#ifdef SDK_TS
#ifdef FIRM_DISABLE_CR_AT_WARMBOOT
@0: bl PXI_RecvByIntf
cmp r0, #FIRM_PXI_ID_COLDBOOT
cmpne r0, #FIRM_PXI_ID_WARMBOOT
@ -137,12 +138,12 @@ SDK_WEAK_SYMBOL asm void _start( void )
mov r0, #FIRM_PXI_ID_INIT_MMEM
bl PXI_SendByIntf
#else // TWL_PLATFORM_BB
#else // !FIRM_DISABLE_CR_AT_WARMBOOT
//---- initialize Main Memory
bl MIi_InitMainMemCR
#endif // TWL_PLATFORM_BB
#endif // !FIRM_DISABLE_CR_AT_WARMBOOT
#endif // SDK_TS
/* システム制御コプロセッサ初期化 */
bl INITi_InitCoprocessor

14
build/libraries/mi/ARM9/mi_init_mainMemory.c
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@ -87,10 +87,10 @@ asm void MIi_InitMainMemCR( BOOL setCR )
// 非同期モード（CLK固定）でコマンド発行しても大丈夫
ldr r3, =HW_WRAM_AREA - 2
bl MIi_InitMainMemCRCore
#ifdef TWL_PLATFORM_TS
ldr r3, =HW_MAIN_MEM_HI_EX_END - 2
#ifdef SDK_TS
ldr r3, =HW_MAIN_MEM + HW_MAIN_MEM_EX_SIZE - 2
bl MIi_InitMainMemCRCore
#endif // TWL_PLATFORM_TS
#endif // SDK_TS
@10:
ldr r3, =REG_EXMEMCNT_ADDR
@ -121,7 +121,7 @@ asm void MIi_InitMainMemCRCore( void )
strh r0, [r3]
strh r1, [r3]
ldrh r3, [r2]
#else // TWL_PLATFORM_TS
#else // SDK_TS
mov r2, lr
ldr r0, =MMEM_TCR0
ldr r1, =MMEM_TCR1
@ -133,7 +133,7 @@ asm void MIi_InitMainMemCRCore( void )
strh r0, [r3]
strh r1, [r3]
strh r2, [r3]
#endif // TWL_PLATFORM_TS
#endif // SDK_TS
// ldmfd sp!, { lr }
bx lr
@ -141,7 +141,7 @@ asm void MIi_InitMainMemCRCore( void )
asm void MIi_GetMainMemCR( MIMmemCR* dest )
{
#ifdef TWL_PLATFORM_TS
#ifdef SDK_TS
ldr r3, =HW_WRAM_AREA - 2
ldr r1, =MMEM_TCR0_R
ldrh r2, [r3]
@ -154,7 +154,7 @@ asm void MIi_GetMainMemCR( MIMmemCR* dest )
strh r1, [r0, #2]
ldr r1, =MMEM_TCR0_R
strh r1, [r0, #0]
#endif // TWL_PLATFORM_TS
#endif // SDK_TS
bx lr
}

36
include/firm/mi/mainMemory.h
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@ -63,9 +63,39 @@ MIMmemCR;
// for TWL-PSRAM
#define MMEM_TCR0 0xFFFF
#define MMEM_TCR1 0xFFDF
#define MMEM_TCR2 0xFFEA
// CR0
#define MMEM_TCR0_SET 0x0001 // セット
#define MMEM_TCR0_VERIFY 0x0000 // ベリファイ
#define MMEM_TCR0_SB1 0xfffe // １固定
#define MMEM_TCR0 (MMEM_TCR0_SET | \
MMEM_TCR0_SB1) // 0xFFFF
#define MMEM_TCR0_R (MMEM_TCR0_VERIFY | \
MMEM_TCR0_SB1) // 0xFFFE
// CR1
#define MMEM_TCR1_PARTIAL_REFRESH_8MB 0x0002 // パーシャルリフレッシュ先頭８ＭＢ
#define MMEM_TCR1_BURST_CONTINUOUS 0x001c // 連続バースト（２２４バイト）
#define MMEM_TCR1_BURST_MODE 0x0000 // バーストモード
#define MMEM_TCR1_DRV_SZ_CENTER 0x00c0 // ドライバーサイズ＝中心
#define MMEM_TCR1_SB1 0xff00 // １固定
#define MMEM_TCR1 (MMEM_TCR1_PARTIAL_REFRESH_8MB | \
MMEM_TCR1_BURST_CONTINUOUS | \
MMEM_TCR1_BURST_MODE | \
MMEM_TCR1_DRV_SZ_CENTER | \
MMEM_TCR1_SB1) // 0xFFDE
// CR2
#define MMEM_TCR2_1ST_R4_W3 0x0002 // １ｓｔＲ／Ｗ ＝ ４／３
#define MMEM_TCR2_REMAIN_PRV_MODE 0x0040 // 前モード保持
#define MMEM_TCR2_WE_LEVEL 0x0080 // ＷＥレベルコントロール
#define MMEM_TCR2_SB1 0xff28 // １固定
#define MMEM_TCR2 (MMEM_TCR2_1ST_R4_W3 | \
MMEM_TCR2_REMAIN_PRV_MODE | \
MMEM_TCR2_WE_LEVEL | \
MMEM_TCR2_SB1) // 0xFFEA
/*---------------------------------------------------------------------------*