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WRAM-B/CのメモリマップをSDKの変更に合わせる。

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git-svn-id: file:///Users/lillianskinner/Downloads/platinum/twl/TwlIPL/trunk@673 b08762b0-b915-fc4b-9d8c-17b2551a87ff
This commit is contained in:
nakasima 2008-02-15 07:10:52 +00:00
parent 3dc7cc8bf2
commit 3f32ef4d6c
2 changed files with 11 additions and 11 deletions
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22
build/components/hyena.TWL/wram_regs/wram_regs.c
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@ -17,24 +17,24 @@
#include <twl/mi.h>
#define HW_HYENA_WRAM_A_OFS (HW_WRAM_A_LTD - HW_WRAM_BASE)
#define HW_HYENA_WRAM_A_OFS_END (HW_WRAM_A_LTD_END - HW_WRAM_BASE)
#define HW_HYENA_WRAM_B_OFS (HW_HYENA_WRAM_A_OFS - HW_WRAM_B_SIZE)
#define HW_HYENA_WRAM_B_OFS_END (HW_HYENA_WRAM_A_OFS)
#define HW_HYENA_WRAM_C_OFS (HW_HYENA_WRAM_B_OFS - HW_WRAM_C_SIZE)
#define HW_HYENA_WRAM_C_OFS_END (HW_HYENA_WRAM_B_OFS)
#define HW_HYENA_WRAM_A_OFS_END (HW_HYENA_WRAM_A_OFS + HW_WRAM_A_SIZE)
#define HW_HYENA_WRAM_B_OFS (HW_WRAM_B - HW_WRAM_BASE)
#define HW_HYENA_WRAM_B_OFS_END (HW_HYENA_WRAM_B_OFS + HW_WRAM_B_SIZE * 2)
#define HW_HYENA_WRAM_C_OFS (HW_WRAM_C - HW_WRAM_BASE)
#define HW_HYENA_WRAM_C_OFS_END (HW_HYENA_WRAM_C_OFS + HW_WRAM_C_SIZE)
// MAP_TS_LTD for hyena
// WRAM-A Lock:ON, Master:ARM7, Enable:Slot0-3(256Kbytes), Address(7):0x037c0000-0x037fffff, Address(9):None
// WRAM-B Lock:ON, Master:ARM7, Enable:Slot7 (32Kbytes), Address(7):0x037b8000-0x037bffff, Address(9):None
// WRAM-B Lock:OFF, Master:ARM9, Enable:Slot0-6(224Kbytes), Address(7):0x03780000-0x037b7fff, Address(9):0x03780000-0x037bffff
// WRAM-C Lock:OFF, Msster:ARM9, Enable:Slot0-7(256Kbytes), Address(7):0x03740000-0x0377ffff, Address(9):0x03740000-0x0377ffff
// WRAM-B Lock:ON, Master:ARM7, Enable:Slot5-7(96Kbytes), Address(7):0x037a8000-0x037bffff, Address(9):None
// WRAM-B Lock:OFF, Master:ARM9, Enable:Slot0-4(160Kbytes), Address(7):0x03740000-0x037bffff, Address(9):0x03740000-0x037bffff
// WRAM-C Lock:OFF, Msster:ARM9, Enable:Slot0-7(256Kbytes), Address(7):0x03700000-0x0373ffff, Address(9):0x03700000-0x0373ffff
// WRAM-0 Master:ARM9, (16Kbytes), Address(7):0x03040000-0x03043fff, Address(9):0x03040000-0x03043fff
// WRAM-1 Master:ARM9, (16Kbytes), Address(7):0x03044000-0x03047fff, Address(9):0x03044000-0x03047fff
// MAP_TS_LTD original
// WRAM-A Lock:ON, Master:ARM7, Enable:Slot0-3(256Kbytes), Address(7):0x037c0000-0x037fffff, Address(9):None
// WRAM-B Lock:OFF, Master:ARM9, Enable:Slot0-7(256Kbytes), Address(7):0x03900000-0x0393ffff, Address(9):0x03900000-0x0393ffff
// WRAM-C Lock:OFF, Msster:ARM9, Enable:Slot0-7(256Kbytes), Address(7):0x03940000-0x0397ffff, Address(9):0x03940000-0x0397ffff
// WRAM-B Lock:OFF, Master:ARM9, Enable:Slot0-7(256Kbytes), Address(7):0x03740000-0x037bffff, Address(9):0x03740000-0x037bffff
// WRAM-C Lock:OFF, Msster:ARM9, Enable:Slot0-7(256Kbytes), Address(7):0x03700000-0x0373ffff, Address(9):0x03700000-0x0373ffff
// WRAM-0 Master:ARM9, (16Kbytes), Address(7):0x03040000-0x03043fff, Address(9):0x03040000-0x03043fff
// WRAM-1 Master:ARM9, (16Kbytes), Address(7):0x03044000-0x03047fff, Address(9):0x03044000-0x03047fff
@ -106,7 +106,7 @@ u32 HYENA_WramReg[0x30/sizeof(u32)] =
// WRAM Lock
(u32)(
(0x0F << 0) |
(0x80 << 8) |
(0xE0 << 8) |
(0x00 << 16) |
// WRAM-0/1

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docs/メモリマップ_ランチャー.vsd
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