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Use improved SDMMC code from bootloader

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This commit is contained in:
RocketRobz 2020-07-14 20:58:52 -06:00
parent 9ac93598db
commit 55474c1d84
2 changed files with 398 additions and 124 deletions
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197
arm7/include/my_sdmmc.h Normal file
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@ -0,0 +1,197 @@
#ifndef __SDMMC_H__
#define __SDMMC_H__
#include <nds/ndstypes.h>
#define DATA32_SUPPORT
#define SDMMC_BASE 0x04004800
#define REG_SDCMD 0x00
#define REG_SDPORTSEL 0x02
#define REG_SDCMDARG 0x04
#define REG_SDCMDARG0 0x04
#define REG_SDCMDARG1 0x06
#define REG_SDSTOP 0x08
#define REG_SDRESP 0x0c
#define REG_SDBLKCOUNT 0x0a
#define REG_SDRESP0 0x0c
#define REG_SDRESP1 0x0e
#define REG_SDRESP2 0x10
#define REG_SDRESP3 0x12
#define REG_SDRESP4 0x14
#define REG_SDRESP5 0x16
#define REG_SDRESP6 0x18
#define REG_SDRESP7 0x1a
#define REG_SDSTATUS0 0x1c
#define REG_SDSTATUS1 0x1e
#define REG_SDIRMASK0 0x20
#define REG_SDIRMASK1 0x22
#define REG_SDCLKCTL 0x24
#define REG_SDBLKLEN 0x26
#define REG_SDOPT 0x28
#define REG_SDFIFO 0x30
#define REG_SDDATACTL 0xd8
#define REG_SDRESET 0xe0
#define REG_SDPROTECTED 0xf6 //bit 0 determines if sd is protected or not?
#define REG_SDDATACTL32 0x100
#define REG_SDBLKLEN32 0x104
#define REG_SDBLKCOUNT32 0x108
#define REG_SDFIFO32 0x10C
#define REG_CLK_AND_WAIT_CTL 0x138
#define REG_RESET_SDIO 0x1e0
//The below defines are from linux kernel drivers/mmc tmio_mmc.h.
/* Definitions for values the CTRL_STATUS register can take. */
#define TMIO_STAT0_CMDRESPEND 0x0001
#define TMIO_STAT0_DATAEND 0x0004
#define TMIO_STAT0_CARD_REMOVE 0x0008
#define TMIO_STAT0_CARD_INSERT 0x0010
#define TMIO_STAT0_SIGSTATE 0x0020
#define TMIO_STAT0_WRPROTECT 0x0080
#define TMIO_STAT0_CARD_REMOVE_A 0x0100
#define TMIO_STAT0_CARD_INSERT_A 0x0200
#define TMIO_STAT0_SIGSTATE_A 0x0400
#define TMIO_STAT1_CMD_IDX_ERR 0x0001
#define TMIO_STAT1_CRCFAIL 0x0002
#define TMIO_STAT1_STOPBIT_ERR 0x0004
#define TMIO_STAT1_DATATIMEOUT 0x0008
#define TMIO_STAT1_RXOVERFLOW 0x0010
#define TMIO_STAT1_TXUNDERRUN 0x0020
#define TMIO_STAT1_CMDTIMEOUT 0x0040
#define TMIO_STAT1_RXRDY 0x0100
#define TMIO_STAT1_TXRQ 0x0200
#define TMIO_STAT1_ILL_FUNC 0x2000
#define TMIO_STAT1_CMD_BUSY 0x4000
#define TMIO_STAT1_ILL_ACCESS 0x8000
#define SDMC_NORMAL 0x00000000
#define SDMC_ERR_COMMAND 0x00000001
#define SDMC_ERR_CRC 0x00000002
#define SDMC_ERR_END 0x00000004
#define SDMC_ERR_TIMEOUT 0x00000008
#define SDMC_ERR_FIFO_OVF 0x00000010
#define SDMC_ERR_FIFO_UDF 0x00000020
#define SDMC_ERR_WP 0x00000040
#define SDMC_ERR_ABORT 0x00000080
#define SDMC_ERR_FPGA_TIMEOUT 0x00000100
#define SDMC_ERR_PARAM 0x00000200
#define SDMC_ERR_R1_STATUS 0x00000800
#define SDMC_ERR_NUM_WR_SECTORS 0x00001000
#define SDMC_ERR_RESET 0x00002000
#define SDMC_ERR_ILA 0x00004000
#define SDMC_ERR_INFO_DETECT 0x00008000
#define SDMC_STAT_ERR_UNKNOWN 0x00080000
#define SDMC_STAT_ERR_CC 0x00100000
#define SDMC_STAT_ERR_ECC_FAILED 0x00200000
#define SDMC_STAT_ERR_CRC 0x00800000
#define SDMC_STAT_ERR_OTHER 0xf9c70008
#define TMIO_MASK_ALL 0x837f031d
#define TMIO_MASK_GW (TMIO_STAT1_ILL_ACCESS | TMIO_STAT1_CMDTIMEOUT | TMIO_STAT1_TXUNDERRUN | TMIO_STAT1_RXOVERFLOW | \
TMIO_STAT1_DATATIMEOUT | TMIO_STAT1_STOPBIT_ERR | TMIO_STAT1_CRCFAIL | TMIO_STAT1_CMD_IDX_ERR)
#define TMIO_MASK_READOP (TMIO_STAT1_RXRDY | TMIO_STAT1_DATAEND)
#define TMIO_MASK_WRITEOP (TMIO_STAT1_TXRQ | TMIO_STAT1_DATAEND)
typedef struct mmcdevice {
u8* rData;
const u8* tData;
u32 size;
u32 startOffset;
u32 endOffset;
u32 error;
u16 stat0;
u16 stat1;
u32 ret[4];
u32 initarg;
u32 isSDHC;
u32 clk;
u32 SDOPT;
u32 devicenumber;
u32 total_size; //size in sectors of the device
u32 res;
} mmcdevice;
enum {
MMC_DEVICE_SDCARD,
MMC_DEVICE_NAND,
};
void my_sdmmc_controller_init(bool force_init);
void my_sdmmc_initirq();
int my_sdmmc_cardinserted();
int my_sdmmc_sdcard_init();
int my_sdmmc_nand_init();
void my_sdmmc_get_cid(int devicenumber, u32 *cid);
static inline void sdmmc_nand_cid( u32 *cid) {
my_sdmmc_get_cid(MMC_DEVICE_NAND,cid);
}
static inline void sdmmc_sdcard_cid( u32 *cid) {
my_sdmmc_get_cid(MMC_DEVICE_SDCARD,cid);
}
int my_sdmmc_sdcard_readsectors(u32 sector_no, u32 numsectors, void *out);
int my_sdmmc_sdcard_writesectors(u32 sector_no, u32 numsectors, void *in);
int my_sdmmc_nand_readsectors(u32 sector_no, u32 numsectors, void *out);
int my_sdmmc_nand_writesectors(u32 sector_no, u32 numsectors, void *in);
extern u32 sdmmc_cid[];
extern int sdmmc_curdevice;
//---------------------------------------------------------------------------------
static inline u16 sdmmc_read16(u16 reg) {
//---------------------------------------------------------------------------------
return *(vu16*)(SDMMC_BASE + reg);
}
//---------------------------------------------------------------------------------
static inline void sdmmc_write16(u16 reg, u16 val) {
//---------------------------------------------------------------------------------
*(vu16*)(SDMMC_BASE + reg) = val;
}
//---------------------------------------------------------------------------------
static inline u32 sdmmc_read32(u16 reg) {
//---------------------------------------------------------------------------------
return *(vu32*)(SDMMC_BASE + reg);
}
//---------------------------------------------------------------------------------
static inline void sdmmc_write32(u16 reg, u32 val) {
//---------------------------------------------------------------------------------
*(vu32*)(SDMMC_BASE + reg) = val;
}
//---------------------------------------------------------------------------------
static inline void sdmmc_mask16(u16 reg, u16 clear, u16 set) {
//---------------------------------------------------------------------------------
u16 val = sdmmc_read16(reg);
val &= ~clear;
val |= set;
sdmmc_write16(reg, val);
}
//---------------------------------------------------------------------------------
static inline void setckl(u32 data) {
//---------------------------------------------------------------------------------
sdmmc_mask16(REG_SDCLKCTL, 0x100, 0);
sdmmc_mask16(REG_SDCLKCTL, 0x2FF, data & 0x2FF);
sdmmc_mask16(REG_SDCLKCTL, 0x0, 0x100);
}
#endif

325
arm7/source/my_sdmmc.c
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@ -1,6 +1,6 @@
#include <nds/system.h>
#include <nds/bios.h>
#include <nds/arm7/sdmmc.h>
#include "my_sdmmc.h"
#include <nds/interrupts.h>
#include <nds/fifocommon.h>
#include <nds/fifomessages.h>
@ -42,132 +42,190 @@ void my_setTarget(struct mmcdevice *ctx) {
//---------------------------------------------------------------------------------
void my_sdmmc_send_command(struct mmcdevice *ctx, uint32_t cmd, uint32_t args) {
//---------------------------------------------------------------------------------
int i;
bool getSDRESP = (cmd << 15) >> 31;
uint16_t flags = (cmd << 15) >> 31;
const bool readdata = cmd & 0x20000;
const bool writedata = cmd & 0x40000;
const bool getSDRESP = (cmd << 15) >> 31;
u16 flags = (cmd << 15) >> 31;
const bool readdata = cmd & 0x20000;
const bool writedata = cmd & 0x40000;
if(readdata || writedata)
{
flags |= TMIO_STAT0_DATAEND;
}
if(readdata || writedata)
{
flags |= TMIO_STAT0_DATAEND;
}
ctx->error = 0;
while((sdmmc_read16(REG_SDSTATUS1) & TMIO_STAT1_CMD_BUSY)); //mmc working?
sdmmc_write16(REG_SDIRMASK0,0);
sdmmc_write16(REG_SDIRMASK1,0);
sdmmc_write16(REG_SDSTATUS0,0);
sdmmc_write16(REG_SDSTATUS1,0);
ctx->error = 0;
while((sdmmc_read16(REG_SDSTATUS1) & TMIO_STAT1_CMD_BUSY)); //mmc working?
sdmmc_write16(REG_SDIRMASK0,0);
sdmmc_write16(REG_SDIRMASK1,0);
sdmmc_write16(REG_SDSTATUS0,0);
sdmmc_write16(REG_SDSTATUS1,0);
sdmmc_mask16(REG_SDDATACTL32,0x1800,0x400); // Disable TX32RQ and RX32RDY IRQ. Clear fifo.
sdmmc_write16(REG_SDCMDARG0,args &0xFFFF);
sdmmc_write16(REG_SDCMDARG1,args >> 16);
sdmmc_write16(REG_SDCMD,cmd &0xFFFF);
u32 size = ctx->size;
const u16 blkSize = sdmmc_read16(REG_SDBLKLEN32);
u32 *rDataPtr32 = (u32*)ctx->rData;
u8 *rDataPtr8 = ctx->rData;
const u32 *tDataPtr32 = (u32*)ctx->tData;
const u8 *tDataPtr8 = ctx->tData;
bool rUseBuf = ( NULL != rDataPtr32 );
bool tUseBuf = ( NULL != tDataPtr32 );
u16 status0 = 0;
while(1)
{
volatile u16 status1 = sdmmc_read16(REG_SDSTATUS1);
#ifdef DATA32_SUPPORT
// if(readdata)sdmmc_mask16(REG_DATACTL32, 0x1000, 0x800);
// if(writedata)sdmmc_mask16(REG_DATACTL32, 0x800, 0x1000);
// sdmmc_mask16(REG_DATACTL32,0x1800,2);
volatile u16 ctl32 = sdmmc_read16(REG_SDDATACTL32);
if((ctl32 & 0x100))
#else
sdmmc_mask16(REG_DATACTL32,0x1800,0);
if((status1 & TMIO_STAT1_RXRDY))
#endif
sdmmc_write16(REG_SDCMDARG0,args &0xFFFF);
sdmmc_write16(REG_SDCMDARG1,args >> 16);
sdmmc_write16(REG_SDCMD,cmd &0xFFFF);
{
if(readdata)
{
if(rUseBuf)
{
sdmmc_mask16(REG_SDSTATUS1, TMIO_STAT1_RXRDY, 0);
if(size >= blkSize)
{
#ifdef DATA32_SUPPORT
if(!((u32)rDataPtr32 & 3))
{
for(u32 i = 0; i < blkSize; i += 4)
{
*rDataPtr32++ = sdmmc_read32(REG_SDFIFO32);
}
}
else
{
for(u32 i = 0; i < blkSize; i += 4)
{
u32 data = sdmmc_read32(REG_SDFIFO32);
*rDataPtr8++ = data;
*rDataPtr8++ = data >> 8;
*rDataPtr8++ = data >> 16;
*rDataPtr8++ = data >> 24;
}
}
#else
if(!((u32)rDataPtr16 & 1))
{
for(u32 i = 0; i < blkSize; i += 4)
{
*rDataPtr16++ = sdmmc_read16(REG_SDFIFO);
}
}
else
{
for(u32 i = 0; i < blkSize; i += 4)
{
u16 data = sdmmc_read16(REG_SDFIFO);
*rDataPtr8++ = data;
*rDataPtr8++ = data >> 8;
}
}
#endif
size -= blkSize;
}
}
uint32_t size = ctx->size;
uint16_t *dataPtr = (uint16_t*)ctx->data;
uint32_t *dataPtr32 = (uint32_t*)ctx->data;
bool useBuf = ( NULL != dataPtr );
bool useBuf32 = (useBuf && (0 == (3 & ((uint32_t)dataPtr))));
uint16_t status0 = 0;
while(1) {
volatile uint16_t status1 = sdmmc_read16(REG_SDSTATUS1);
sdmmc_mask16(REG_SDDATACTL32, 0x800, 0);
}
}
#ifdef DATA32_SUPPORT
volatile uint16_t ctl32 = sdmmc_read16(REG_SDDATACTL32);
if((ctl32 & 0x100))
if(!(ctl32 & 0x200))
#else
if((status1 & TMIO_STAT1_RXRDY))
if((status1 & TMIO_STAT1_TXRQ))
#endif
{
if(readdata) {
if(useBuf) {
sdmmc_mask16(REG_SDSTATUS1, TMIO_STAT1_RXRDY, 0);
if(size > 0x1FF) {
#ifdef DATA32_SUPPORT
if(useBuf32) {
for(i = 0; i<0x200; i+=4) {
*dataPtr32++ = sdmmc_read32(REG_SDFIFO32);
}
} else {
#endif
for(i = 0; i<0x200; i+=2) {
*dataPtr++ = sdmmc_read16(REG_SDFIFO);
}
#ifdef DATA32_SUPPORT
}
#endif
size -= 0x200;
}
}
{
if(writedata)
{
if(tUseBuf)
{
sdmmc_mask16(REG_SDSTATUS1, TMIO_STAT1_TXRQ, 0);
if(size >= blkSize)
{
#ifdef DATA32_SUPPORT
if(!((u32)tDataPtr32 & 3))
{
for(u32 i = 0; i < blkSize; i += 4)
{
sdmmc_write32(REG_SDFIFO32, *tDataPtr32++);
}
}
else
{
for(u32 i = 0; i < blkSize; i += 4)
{
u32 data = *tDataPtr8++;
data |= (u32)*tDataPtr8++ << 8;
data |= (u32)*tDataPtr8++ << 16;
data |= (u32)*tDataPtr8++ << 24;
sdmmc_write32(REG_SDFIFO32, data);
}
}
#else
if(!((u32)tDataPtr16 & 1))
{
for(u32 i = 0; i < blkSize; i += 2)
{
sdmmc_write16(REG_SDFIFO, *tDataPtr16++);
}
}
else
{
for(u32 i = 0; i < blkSize; i += 2)
{
u16 data = *tDataPtr8++;
data |= (u16)(*tDataPtr8++ << 8);
sdmmc_write16(REG_SDFIFO, data);
}
}
#endif
size -= blkSize;
}
}
sdmmc_mask16(REG_SDDATACTL32, 0x800, 0);
}
}
#ifdef DATA32_SUPPORT
if(!(ctl32 & 0x200))
#else
if((status1 & TMIO_STAT1_TXRQ))
#endif
{
if(writedata) {
if(useBuf) {
sdmmc_mask16(REG_SDSTATUS1, TMIO_STAT1_TXRQ, 0);
//sdmmc_write16(REG_SDSTATUS1,~TMIO_STAT1_TXRQ);
if(size > 0x1FF) {
#ifdef DATA32_SUPPORT
for(i = 0; i<0x200; i+=4) {
sdmmc_write32(REG_SDFIFO32,*dataPtr32++);
}
#else
for(i = 0; i<0x200; i+=2) {
sdmmc_write16(REG_SDFIFO,*dataPtr++);
}
#endif
size -= 0x200;
}
}
sdmmc_mask16(REG_SDDATACTL32, 0x1000, 0);
}
}
if(status1 & TMIO_MASK_GW)
{
ctx->error |= 4;
break;
}
sdmmc_mask16(REG_SDDATACTL32, 0x1000, 0);
}
}
if(status1 & TMIO_MASK_GW) {
ctx->error |= 4;
break;
}
if(!(status1 & TMIO_STAT1_CMD_BUSY))
{
status0 = sdmmc_read16(REG_SDSTATUS0);
if(sdmmc_read16(REG_SDSTATUS0) & TMIO_STAT0_CMDRESPEND)
{
ctx->error |= 0x1;
}
if(status0 & TMIO_STAT0_DATAEND)
{
ctx->error |= 0x2;
}
if(!(status1 & TMIO_STAT1_CMD_BUSY)) {
status0 = sdmmc_read16(REG_SDSTATUS0);
if(sdmmc_read16(REG_SDSTATUS0) & TMIO_STAT0_CMDRESPEND) {
ctx->error |= 0x1;
}
if(status0 & TMIO_STAT0_DATAEND) {
ctx->error |= 0x2;
}
if((status0 & flags) == flags)
break;
}
}
ctx->stat0 = sdmmc_read16(REG_SDSTATUS0);
ctx->stat1 = sdmmc_read16(REG_SDSTATUS1);
sdmmc_write16(REG_SDSTATUS0,0);
sdmmc_write16(REG_SDSTATUS1,0);
if((status0 & flags) == flags)
break;
}
}
ctx->stat0 = sdmmc_read16(REG_SDSTATUS0);
ctx->stat1 = sdmmc_read16(REG_SDSTATUS1);
sdmmc_write16(REG_SDSTATUS0,0);
sdmmc_write16(REG_SDSTATUS1,0);
if(getSDRESP != 0) {
ctx->ret[0] = sdmmc_read16(REG_SDRESP0) | (sdmmc_read16(REG_SDRESP1) << 16);
ctx->ret[1] = sdmmc_read16(REG_SDRESP2) | (sdmmc_read16(REG_SDRESP3) << 16);
ctx->ret[2] = sdmmc_read16(REG_SDRESP4) | (sdmmc_read16(REG_SDRESP5) << 16);
ctx->ret[3] = sdmmc_read16(REG_SDRESP6) | (sdmmc_read16(REG_SDRESP7) << 16);
}
if(getSDRESP != 0)
{
ctx->ret[0] = (u32)(sdmmc_read16(REG_SDRESP0) | (sdmmc_read16(REG_SDRESP1) << 16));
ctx->ret[1] = (u32)(sdmmc_read16(REG_SDRESP2) | (sdmmc_read16(REG_SDRESP3) << 16));
ctx->ret[2] = (u32)(sdmmc_read16(REG_SDRESP4) | (sdmmc_read16(REG_SDRESP5) << 16));
ctx->ret[3] = (u32)(sdmmc_read16(REG_SDRESP6) | (sdmmc_read16(REG_SDRESP7) << 16));
}
}
@ -272,8 +330,9 @@ static u32 calcSDSize(u8* csd, int type) {
//---------------------------------------------------------------------------------
int my_sdmmc_sdcard_init() {
//---------------------------------------------------------------------------------
// We need to send at least 74 clock pulses.
my_setTarget(&deviceSD);
swiDelay(0xF000);
swiDelay(0x1980); // ~75-76 clocks
// card reset
my_sdmmc_send_command(&deviceSD,0,0);
@ -309,9 +368,10 @@ int my_sdmmc_sdcard_init() {
my_sdmmc_send_command(&deviceSD,0x10609,deviceSD.initarg << 0x10);
if (deviceSD.error & 0x4) return -1;
// Command Class 10 support
const bool cmd6Supported = ((u8*)deviceSD.ret)[10] & 0x40;
deviceSD.total_size = calcSDSize((u8*)&deviceSD.ret[0],-1);
deviceSD.clk = 1;
setckl(1);
setckl(0x201); // 16.756991 MHz
my_sdmmc_send_command(&deviceSD,0x10507,deviceSD.initarg << 0x10);
if (deviceSD.error & 0x4) return -1;
@ -326,18 +386,35 @@ int my_sdmmc_sdcard_init() {
// CMD55
my_sdmmc_send_command(&deviceSD,0x10437,deviceSD.initarg << 0x10);
if (deviceSD.error & 0x4) return -1;
if (deviceSD.error & 0x4) return -7;
deviceSD.SDOPT = 1;
my_sdmmc_send_command(&deviceSD,0x10446,0x2);
if (deviceSD.error & 0x4) return -1;
if (deviceSD.error & 0x4) return -8;
sdmmc_mask16(REG_SDOPT, 0x8000, 0); // Switch to 4 bit mode.
// TODO: CMD6 to switch to high speed mode.
if(cmd6Supported)
{
sdmmc_write16(REG_SDSTOP,0);
sdmmc_write16(REG_SDBLKLEN32,64);
sdmmc_write16(REG_SDBLKLEN,64);
deviceSD.rData = NULL;
deviceSD.size = 64;
my_sdmmc_send_command(&deviceSD,0x31C06,0x80FFFFF1);
sdmmc_write16(REG_SDBLKLEN,512);
if(deviceSD.error & 0x4) return -9;
deviceSD.clk = 0x200; // 33.513982 MHz
setckl(0x200);
}
else deviceSD.clk = 0x201; // 16.756991 MHz
my_sdmmc_send_command(&deviceSD,0x1040D,deviceSD.initarg << 0x10);
if (deviceSD.error & 0x4) return -1;
if (deviceSD.error & 0x4) return -9;
my_sdmmc_send_command(&deviceSD,0x10410,0x200);
if (deviceSD.error & 0x4) return -1;
deviceSD.clk |= 0x200;
if (deviceSD.error & 0x4) return -10;
return 0;
@ -408,7 +485,7 @@ int my_sdmmc_readsectors(struct mmcdevice *device, u32 sector_no, u32 numsectors
#endif
sdmmc_write16(REG_SDBLKCOUNT,numsectors);
device->data = out;
device->rData = out;
device->size = numsectors << 9;
my_sdmmc_send_command(device,0x33C12,sector_no);
my_setTarget(&deviceSD);
@ -429,7 +506,7 @@ int my_sdmmc_writesectors(struct mmcdevice *device, u32 sector_no, u32 numsector
#endif
sdmmc_write16(REG_SDBLKCOUNT,numsectors);
device->data = in;
device->tData = in;
device->size = numsectors << 9;
my_sdmmc_send_command(device,0x52C19,sector_no);
my_setTarget(&deviceSD);