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183228e28e
Removed the arm7 section Changed the makefile to only use the arm9 stuff Epicpkmn: Fix source/Graphics/GraphicsManager.cpp Co-Authored-By: Pk11 <epicpkmn11@outlook.com> Co-Authored-By: Kaisaan <34224128+Kaisaan@users.noreply.github.com>
262 lines
7.9 KiB
C
262 lines
7.9 KiB
C
/*---------------------------------------------------------------------------------
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Copyright (C) 2005
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Dave Murphy (WinterMute)
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This software is provided 'as-is', without any express or implied
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warranty. In no event will the authors be held liable for any
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damages arising from the use of this software.
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Permission is granted to anyone to use this software for any
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purpose, including commercial applications, and to alter it and
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redistribute it freely, subject to the following restrictions:
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1. The origin of this software must not be misrepresented; you
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must not claim that you wrote the original software. If you use
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this software in a product, an acknowledgment in the product
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documentation would be appreciated but is not required.
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2. Altered source versions must be plainly marked as such, and
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must not be misrepresented as being the original software.
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3. This notice may not be removed or altered from any source
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distribution.
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---------------------------------------------------------------------------------*/
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/*
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#include <nds/ndstypes.h>
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#include <nds/memory.h>
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#include <nds/arm9/video.h>
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#include <nds/arm9/console.h>
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#include <nds/arm9/exceptions.h>
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#include <nds/arm9/background.h>
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*/
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#include <nds.h>
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#include <stdio.h>
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//---------------------------------------------------------------------------------
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unsigned long ARMShiftO(unsigned long value,unsigned char shift) {
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//---------------------------------------------------------------------------------
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// no shift at all
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if (shift == 0x0B) return value ;
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int index ;
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if (shift & 0x01) {
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// shift index is a register
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index = exceptionRegisters[(shift >> 4) & 0x0F];
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} else {
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// constant shift index
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index = ((shift >> 3) & 0x1F) ;
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} ;
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int i ;
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bool isN ;
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switch (shift & 0x06) {
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case 0x00:
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// logical left
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return (value << index) ;
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case 0x02:
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// logical right
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return (value >> index) ;
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case 0x04:
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// arithmetical right
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isN = (value & 0x80000000) ;
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value = value >> index ;
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if (isN) {
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for (i=31;i>31-index;i--) {
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value = value | (1 << i) ;
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} ;
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} ;
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return value ;
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case 0x06:
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// rotate right
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index = index & 0x1F;
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value = (value >> index) | (value << (32-index));
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return value;
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};
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return value;
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}
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//---------------------------------------------------------------------------------
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u32 getExceptionAddressO( u32 opcodeAddress, u32 thumbState) {
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//---------------------------------------------------------------------------------
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int Rf, Rb, Rd, Rn, Rm;
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if (thumbState) {
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// Thumb
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unsigned short opcode = *(unsigned short *)opcodeAddress ;
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// ldr r,[pc,###] 01001ddd ffffffff
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// ldr r,[r,r] 0101xx0f ffbbbddd
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// ldrsh 0101xx1f ffbbbddd
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// ldr r,[r,imm] 011xxfff ffbbbddd
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// ldrh 1000xfff ffbbbddd
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// ldr r,[sp,###] 1001xddd ffffffff
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// push 1011x10l llllllll
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// ldm 1100xbbb llllllll
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if ((opcode & 0xF800) == 0x4800) {
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// ldr r,[pc,###]
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s8 offset = opcode & 0xff;
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return exceptionRegisters[15] + offset;
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} else if ((opcode & 0xF200) == 0x5000) {
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// ldr r,[r,r]
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Rb = (opcode >> 3) & 0x07 ;
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Rf = (opcode >> 6) & 0x07 ;
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return exceptionRegisters[Rb] + exceptionRegisters[Rf];
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} else if ((opcode & 0xF200) == 0x5200) {
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// ldrsh
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Rb = (opcode >> 3) & 0x07;
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Rf = (opcode >> 6) & 0x03;
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return exceptionRegisters[Rb] + exceptionRegisters[Rf];
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} else if ((opcode & 0xE000) == 0x6000) {
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// ldr r,[r,imm]
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Rb = (opcode >> 3) & 0x07;
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Rf = (opcode >> 6) & 0x1F ;
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return exceptionRegisters[Rb] + (Rf << 2);
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} else if ((opcode & 0xF000) == 0x8000) {
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// ldrh
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Rb = (opcode >> 3) & 0x07 ;
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Rf = (opcode >> 6) & 0x1F ;
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return exceptionRegisters[Rb] + (Rf << 2);
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} else if ((opcode & 0xF000) == 0x9000) {
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// ldr r,[sp,#imm]
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s8 offset = opcode & 0xff;
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return exceptionRegisters[13] + offset;
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} else if ((opcode & 0xF700) == 0xB500) {
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// push/pop
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return exceptionRegisters[13];
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} else if ((opcode & 0xF000) == 0xC000) {
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// ldm/stm
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Rd = (opcode >> 8) & 0x07;
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return exceptionRegisters[Rd];
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}
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} else {
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// arm32
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unsigned long opcode = *(unsigned long *)opcodeAddress ;
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// SWP xxxx0001 0x00nnnn dddd0000 1001mmmm
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// STR/LDR xxxx01xx xxxxnnnn ddddffff ffffffff
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// STRH/LDRH xxxx000x x0xxnnnn dddd0000 1xx1mmmm
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// STRH/LDRH xxxx000x x1xxnnnn ddddffff 1xx1ffff
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// STM/LDM xxxx100x xxxxnnnn llllllll llllllll
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if ((opcode & 0x0FB00FF0) == 0x01000090) {
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// SWP
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Rn = (opcode >> 16) & 0x0F;
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return exceptionRegisters[Rn];
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} else if ((opcode & 0x0C000000) == 0x04000000) {
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// STR/LDR
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Rn = (opcode >> 16) & 0x0F;
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if (opcode & 0x02000000) {
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// Register offset
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Rm = opcode & 0x0F;
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if (opcode & 0x01000000) {
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unsigned short shift = (unsigned short)((opcode >> 4) & 0xFF) ;
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// pre indexing
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long Offset = ARMShiftO(exceptionRegisters[Rm],shift);
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// add or sub the offset depending on the U-Bit
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return exceptionRegisters[Rn] + ((opcode & 0x00800000)?Offset:-Offset);
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} else {
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// post indexing
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return exceptionRegisters[Rn];
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}
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} else {
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// Immediate offset
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unsigned long Offset = (opcode & 0xFFF) ;
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if (opcode & 0x01000000) {
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// pre indexing
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// add or sub the offset depending on the U-Bit
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return exceptionRegisters[Rn] + ((opcode & 0x00800000)?Offset:-Offset);
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} else {
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// post indexing
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return exceptionRegisters[Rn];
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}
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}
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} else if ((opcode & 0x0E400F90) == 0x00000090) {
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// LDRH/STRH with register Rm
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Rn = (opcode >> 16) & 0x0F;
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Rd = (opcode >> 12) & 0x0F;
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Rm = opcode & 0x0F;
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unsigned short shift = (unsigned short)((opcode >> 4) & 0xFF);
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long Offset = ARMShiftO(exceptionRegisters[Rm],shift);
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// add or sub the offset depending on the U-Bit
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return exceptionRegisters[Rn] + ((opcode & 0x00800000)?Offset:-Offset);
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} else if ((opcode & 0x0E400F90) == 0x00400090) {
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// LDRH/STRH with immediate offset
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Rn = (opcode >> 16) & 0x0F;
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Rd = (opcode >> 12) & 0x0F;
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unsigned long Offset = (opcode & 0xF) | ((opcode & 0xF00)>>8) ;
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// add or sub the offset depending on the U-Bit
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return exceptionRegisters[Rn] + ((opcode & 0x00800000)?Offset:-Offset) ;
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} else if ((opcode & 0x0E000000) == 0x08000000) {
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// LDM/STM
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Rn = (opcode >> 16) & 0x0F;
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return exceptionRegisters[Rn];
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}
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}
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return 0;
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}
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static const char *registerNames[] =
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{ "r0","r1","r2","r3","r4","r5","r6","r7",
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"r8 ","r9 ","r10","r11","r12","sp ","lr ","pc " };
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extern const char __itcm_start[];
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//---------------------------------------------------------------------------------
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void customHandler() {
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//---------------------------------------------------------------------------------
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consoleDemoInit();
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BG_PALETTE[0] = RGB15(31,0,0);
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BG_PALETTE[255] = RGB15(31,31,31);
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iprintf("\x1b[5CGuru Meditation Error!\n");
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u32 currentMode = getCPSR() & 0x1f;
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u32 thumbState = ((*(u32*)0x027FFD90) & 0x20);
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u32 codeAddress, exceptionAddress = 0;
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int offset = 8;
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if ( currentMode == 0x17 ) {
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iprintf ("\x1b[10Cdata abort!\n\n");
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codeAddress = exceptionRegisters[15] - offset;
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if ( (codeAddress > 0x02000000 && codeAddress < 0x02400000) ||
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(codeAddress > (u32)__itcm_start && codeAddress < (u32)(__itcm_start + 32768)) )
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exceptionAddress = getExceptionAddressO( codeAddress, thumbState);
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else
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exceptionAddress = codeAddress;
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} else {
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if (thumbState)
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offset = 2;
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else
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offset = 4;
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iprintf("\x1b[5Cundefined instruction!\n\n");
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codeAddress = exceptionRegisters[15] - offset;
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exceptionAddress = codeAddress;
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}
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iprintf(" pc: %08X addr: %08X\n\n",codeAddress,exceptionAddress);
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int i;
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for ( i=0; i < 8; i++ ) {
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iprintf( " %s: %08X %s: %08X\n",
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registerNames[i], exceptionRegisters[i],
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registerNames[i+8],exceptionRegisters[i+8]);
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}
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iprintf("\x1b[2J");
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u32 *stack = (u32 *)exceptionRegisters[13];
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for ( i=0; i<24; i++ ) {
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iprintf( "\x1b[%d;2H%08X: %08X %08X", i, (u32)&stack[i*2],stack[i*2], stack[(i*2)+1] );
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}
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while(1) swiWaitForVBlank();
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}
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