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https://github.com/coderkei/akmenu-next.git
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135 lines
3.4 KiB
C
135 lines
3.4 KiB
C
/*
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SuperCard DSONE
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Card IO routines
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Copyright (C) 2006 SuperCard
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Copyright (C) 2023 lifehackerhansol
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SPDX-License-Identifier: Zlib
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*/
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#pragma once
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <nds/ndstypes.h>
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#include "libtwl_card.h"
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#ifndef NULL
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#define NULL 0
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#endif
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// libtwl workaround
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// Certain DSTT clones need bytewise access to MCCMD
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#define REG_SCDS_MCCMD ((vu8*)®_MCCMD0)
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// SCDS defines
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// SCDS ROMCTRL flags
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#define SCDS_CTRL_BASE (MCCNT1_ENABLE | MCCNT1_RESET_OFF | MCCNT1_LATENCY2(24) | MCCNT1_LATENCY1(0))
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#define SCDS_CTRL_READ_4B (SCDS_CTRL_BASE | MCCNT1_LEN_4)
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#define SCDS_CTRL_READ_512B (SCDS_CTRL_BASE | MCCNT1_LEN_512)
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#define SCDS_CTRL_WRITE_4B (SCDS_CTRL_BASE | MCCNT1_DIR_WRITE | MCCNT1_LEN_4)
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#define SCDS_CTRL_WRITE_512B (SCDS_CTRL_BASE | MCCNT1_DIR_WRITE | MCCNT1_LEN_512)
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#define SCDS_CTRL_SD_LOW_CLK_LATENCY 0x1000
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// SCDS CARD_COMMANDs
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/*
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SRAM commands
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Command structure:
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AA BB BB BB BB 00 00 00
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AA = command
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BBBBBBBB = address
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*/
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#define SCDS_CMD_SRAM_READ_DATA (0x70)
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#define SCDS_CMD_SRAM_WRITE_DATA (0x71)
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// FIFO commands
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#define SCDS_CMD_FIFO_BUSY (0x80)
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#define SCDS_CMD_FIFO_READ_DATA (0x81)
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#define SCDS_CMD_FIFO_WRITE_DATA (0x82)
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/*
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SD host modes
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Used with 0x51 command, see below
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*/
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enum SCDS_SD_HOST_MODES {
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SCDS_SD_HOST_NORESPONSE = 0,
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SCDS_SD_HOST_READ_4B = 1,
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SCDS_SD_HOST_READ_4B_MULTI = 2, // use mode 3 to continue this read
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SCDS_SD_HOST_NEXT_4B = 3,
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SCDS_SD_HOST_SEND_CLK = 4,
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SCDS_SD_HOST_SEND_STOP_CLK = 5,
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SCDS_SD_HOST_READ_DATABLOCK = 6,
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SCDS_SD_HOST_NEXT_DATABLOCK = 7,
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SCDS_SD_HOST_CMD17_READ_DATA = 8, // Send SDIO CMD17 & read data
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SCDS_SD_HOST_CMD18_READ_DATA = 9, // Send SDIO CMD18 & read data until stop
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SCDS_SD_HOST_COMMIT_FIFO_DATA = 0xA, // commit data in FIFO to SD card
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SCDS_SD_HOST_CMD24_WRITE_DATA = 0xB, // Send SDIO CMD24 & send data in SRAM buffer
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SCDS_SD_HOST_WAIT_BUSY = 0xC // wait until data transfer ends
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};
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/*
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SD host related commands
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Note:
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While this is where the SDIO happens, it isn't always SDIO
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Thus, it can sometimes be 0
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Command structure:
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51 AA AA AA AA BB CC 00
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AAAAAAAA = SDIO parameter
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BB = SDIO command
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CC = SD host mode, see SCDS_SD_HOST_MODES enum
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*/
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#define SCDS_CMD_SD_HOST_PARAM (0x51)
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// SD host misc commands
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// return 0 == idle
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// return non-0 == not idle
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#define SCDS_CMD_SD_HOST_BUSY (0x50)
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// Gets response of SD_HOST commands, if the sent mode is 1 or 2
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#define SCDS_CMD_SD_HOST_RESPONSE (0x52)
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// Stops SD host data transfer
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#define SCDS_CMD_SD_WRITE_END (0x56)
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// Sends CMD17
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#define SCDS_CMD_SD_READ_SINGLE_BLOCK (0x53)
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// Sends CMD18
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#define SCDS_CMD_SD_READ_MULTI_BLOCK (0x54)
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/*
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SD host control registers
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The 0x5F sets raw registers related to the SD host, which is a single u8.
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Bits:
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0: Reset
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1: Set 400k low clk
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2: Use 0xB7 as alternative of 0x5B for ROM reads
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3: Set SDHC mode
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4-5: 1
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6-7: 0
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*/
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#define SCDS_SD_HOST_REG_RESET BIT(0)
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#define SCDS_SD_HOST_REG_400KHZ_CLK BIT(1)
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#define SCDS_SD_HOST_REG_CLEAN_ROM_MODE BIT(2)
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#define SCDS_SD_HOST_REG_SDHC BIT(3)
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// Command to write to host register
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#define SCDS_CMD_SD_HOST_SET_REGISTER (0x5F)
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// user API
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bool SCDS_SDInitialize(void);
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void SCDS_SDReadSingleSector(u32 sector, void *buffer);
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void SCDS_SDReadMultiSector(u32 sector, void *buffer, u32 num_sectors);
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void SCDS_SDWriteSingleSector(u32 sector, const void *buffer);
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void SCDS_SDWriteMultiSector(u32 sector, const void *buffer, u32 num_sectors);
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#ifdef __cplusplus
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}
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#endif
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