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Work around broken FIFO setup

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Not entirely sure why, but FIFOs were being sent and received AFTER the
interrupts were cleared, causing them to not send.

It's unknown how this ever worked on older libnds/devkitARM, but FIFOs
need interrupts to work.

This workaround, instead, hijacks an area of the ROM header as a
temporary variable to wait for ARM7.
This commit is contained in:
lifehackerhansol 2024-10-13 04:46:43 -07:00
parent fc0e950f34
commit 21b6b529f3
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GPG Key ID: 80FB184AFC0B3B0E
2 changed files with 11 additions and 24 deletions
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3
arm7/source/main.cpp
View File

@ -61,7 +61,8 @@ static void prepairReset() {
REG_IE = 0; REG_IE = 0;
REG_IF = ~0; REG_IF = ~0;
fifoSendValue32(FIFO_USER_01, MENU_MSG_ARM7_READY_BOOT); // instruct arm9 to reset
*((vu32*)0x02FFFE04) = MENU_MSG_ARM7_READY_BOOT;
swiDelay(1); swiDelay(1);
} }

32
arm9/source/launcher/AcekardLauncher.cpp
View File

@ -21,35 +21,21 @@
// 256 UCS-2 characters encoded into UTF-8 can use up to 768 UTF-8 chars // 256 UCS-2 characters encoded into UTF-8 can use up to 768 UTF-8 chars
#define MAX_FILENAME_LENGTH 768 #define MAX_FILENAME_LENGTH 768
// FIFO_CHANNEL_BITS - number of bits used to specify the channel in a packet - default=4
#define FIFO_CHANNEL_BITS 4
#define FIFO_CHANNEL_SHIFT (32 - FIFO_CHANNEL_BITS)
#define FIFO_IMMEDIATEBIT_SHIFT (FIFO_CHANNEL_SHIFT - 2)
#define FIFO_IMMEDIATEBIT (1 << FIFO_IMMEDIATEBIT_SHIFT)
#define FIFO_EXTRABIT_SHIFT (FIFO_CHANNEL_SHIFT - 3)
#define FIFO_EXTRABIT (1 << FIFO_EXTRABIT_SHIFT)
#define FIFO_VALUE32_MASK (FIFO_EXTRABIT - 1)
#define FIFO_PACK_VALUE32(channel, value32) \
(((channel) << FIFO_CHANNEL_SHIFT) | FIFO_IMMEDIATEBIT | (((value32)) & FIFO_VALUE32_MASK))
static void resetAndLoop() { static void resetAndLoop() {
DC_FlushAll();
DC_InvalidateAll();
fifoSendValue32(FIFO_USER_01, MENU_MSG_ARM7_REBOOT);
*((vu32*)0x02FFFE04) = 0;
// Interrupt // Interrupt
REG_IME = 0; REG_IME = 0;
REG_IE = 0; REG_IE = 0;
REG_IF = ~0; REG_IF = ~0;
DC_FlushAll(); // wait for arm7
DC_InvalidateAll(); while (*((vu32*)0x02FFFE04) == 0)
;
fifoSendValue32(FIFO_USER_01, MENU_MSG_ARM7_REBOOT);
while (true) {
while (REG_IPC_FIFO_CR & IPC_FIFO_RECV_EMPTY)
;
u32 res = REG_IPC_FIFO_RX;
if (FIFO_PACK_VALUE32(FIFO_USER_01, MENU_MSG_ARM7_READY_BOOT) == res) break;
}
swiSoftReset(); swiSoftReset();
} }