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fe7fa40869
The ARM backend contains code that tries to optimize compares by replacing them with an existing instruction that sets the flags the same way. This allows it to replace a "cmp" with a "adds", generalizing the code that replaces "cmp" with "sub". It also heuristically disables sinking of instructions that could potentially be used to replace compares (currently only if they're next to each other). Differential revision: https://reviews.llvm.org/D38378 llvm-svn: 322737
115 lines
3.7 KiB
LLVM
115 lines
3.7 KiB
LLVM
; RUN: llc < %s -mtriple=arm-linux -mcpu=generic -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix=ARM
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; RUN: llc < %s -mtriple=thumbv6m-eabi -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix=THUMBV6
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; RUN: llc < %s -mtriple=thumbv7-eabi -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix=THUMBV7
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define i32 @uadd_overflow(i32 %a, i32 %b) #0 {
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%sadd = tail call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 %a, i32 %b)
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%1 = extractvalue { i32, i1 } %sadd, 1
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%2 = zext i1 %1 to i32
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ret i32 %2
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; CHECK-LABEL: uadd_overflow:
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; ARM: adds r[[R0:[0-9]+]], r[[R0]], r[[R1:[0-9]+]]
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; ARM: mov r[[R2:[0-9]+]], #0
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; ARM: adc r[[R0]], r[[R2]], #0
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; THUMBV6: movs r[[R2:[0-9]+]], #0
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; THUMBV6: adds r[[R0:[0-9]+]], r[[R0]], r[[R1:[0-9]+]]
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; THUMBV6: adcs r[[R2]], r[[R2]]
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; THUMBV6: mov r[[R0]], r[[R2]]
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; THUMBV7: adds r[[R0:[0-9]+]], r[[R0]], r[[R1:[0-9]+]]
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; THUMBV7: mov.w r[[R2:[0-9]+]], #0
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; THUMBV7: adc r[[R0]], r[[R2]], #0
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}
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define i32 @sadd_overflow(i32 %a, i32 %b) #0 {
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%sadd = tail call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %a, i32 %b)
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%1 = extractvalue { i32, i1 } %sadd, 1
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%2 = zext i1 %1 to i32
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ret i32 %2
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; CHECK-LABEL: sadd_overflow:
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; ARM: adds r[[R2:[0-9]+]], r[[R0:[0-9]+]], r[[R1:[0-9]+]]
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; ARM: mov r[[R0]], #1
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; ARM: movvc r[[R0]], #0
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; ARM: mov pc, lr
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; THUMBV6: mov r[[R2:[0-9]+]], r[[R0:[0-9]+]]
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; THUMBV6: adds r[[R3:[0-9]+]], r[[R2]], r[[R1:[0-9]+]]
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; THUMBV6: movs r[[R0]], #0
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; THUMBV6: movs r[[R1]], #1
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; THUMBV6: cmp r[[R3]], r[[R2]]
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; THUMBV6: bvc .L[[LABEL:.*]]
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; THUMBV6: mov r[[R0]], r[[R1]]
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; THUMBV6: .L[[LABEL]]:
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; THUMBV7: adds r[[R2:[0-9]+]], r[[R0]], r[[R1:[0-9]+]]
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; THUMBV7: mov.w r[[R0:[0-9]+]], #1
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; THUMBV7: it vc
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; THUMBV7: movvc r[[R0]], #0
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}
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define i32 @usub_overflow(i32 %a, i32 %b) #0 {
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%sadd = tail call { i32, i1 } @llvm.usub.with.overflow.i32(i32 %a, i32 %b)
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%1 = extractvalue { i32, i1 } %sadd, 1
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%2 = zext i1 %1 to i32
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ret i32 %2
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; CHECK-LABEL: usub_overflow:
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; ARM: subs r[[R0:[0-9]+]], r[[R0]], r[[R1:[0-9]+]]
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; ARM: mov r[[R2:[0-9]+]], #0
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; ARM: adc r[[R0]], r[[R2]], #0
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; ARM: rsb r[[R0]], r[[R0]], #1
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; THUMBV6: movs r[[R2:[0-9]+]], #0
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; THUMBV6: subs r[[R0:[0-9]+]], r[[R0]], r[[R1:[0-9]+]]
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; THUMBV6: adcs r[[R2]], r[[R2]]
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; THUMBV6: movs r[[R0]], #1
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; THUMBV6: subs r[[R0]], r[[R0]], r[[R2]]
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; THUMBV7: subs r[[R0:[0-9]+]], r[[R0]], r[[R1:[0-9]+]]
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; THUMBV7: mov.w r[[R2:[0-9]+]], #0
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; THUMBV7: adc r[[R0]], r[[R2]], #0
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; THUMBV7: rsb.w r[[R0]], r[[R0]], #1
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; We should know that the overflow is just 1 bit,
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; no need to clear any other bit
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; CHECK-NOT: and
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}
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define i32 @ssub_overflow(i32 %a, i32 %b) #0 {
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%sadd = tail call { i32, i1 } @llvm.ssub.with.overflow.i32(i32 %a, i32 %b)
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%1 = extractvalue { i32, i1 } %sadd, 1
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%2 = zext i1 %1 to i32
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ret i32 %2
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; CHECK-LABEL: ssub_overflow:
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; ARM: mov r[[R2]], #1
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; ARM: cmp r[[R0]], r[[R1]]
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; ARM: movvc r[[R2]], #0
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; THUMBV6: movs r[[R0]], #0
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; THUMBV6: movs r[[R3:[0-9]+]], #1
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; THUMBV6: cmp r[[R2]], r[[R1:[0-9]+]]
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; THUMBV6: bvc .L[[LABEL:.*]]
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; THUMBV6: mov r[[R0]], r[[R3]]
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; THUMBV6: .L[[LABEL]]:
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; THUMBV7: movs r[[R2:[0-9]+]], #1
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; THUMBV7: cmp r[[R0:[0-9]+]], r[[R1:[0-9]+]]
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; THUMBV7: it vc
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; THUMBV7: movvc r[[R2]], #0
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; THUMBV7: mov r[[R0]], r[[R2]]
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}
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declare { i32, i1 } @llvm.uadd.with.overflow.i32(i32, i32) #1
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declare { i32, i1 } @llvm.sadd.with.overflow.i32(i32, i32) #2
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declare { i32, i1 } @llvm.usub.with.overflow.i32(i32, i32) #3
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declare { i32, i1 } @llvm.ssub.with.overflow.i32(i32, i32) #4
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