mirror of
https://github.com/Gericom/teak-llvm.git
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281 lines
9.7 KiB
C++
281 lines
9.7 KiB
C++
//===-- TeakRegisterInfo.cpp - Teak Register Information ----------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Teak implementation of the MRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "TeakRegisterInfo.h"
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#include "Teak.h"
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#include "TeakFrameLowering.h"
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#include "TeakInstrInfo.h"
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#include "TeakSubtarget.h"
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#include "TeakMachineFunctionInfo.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/RegisterScavenging.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/Type.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/CodeGen/TargetFrameLowering.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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using namespace llvm;
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#define GET_REGINFO_TARGET_DESC
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#include "TeakGenRegisterInfo.inc"
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TeakRegisterInfo::TeakRegisterInfo() : TeakGenRegisterInfo(0) {}
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const MCPhysReg* TeakRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const
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{
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return CSR_SaveList;
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}
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BitVector TeakRegisterInfo::getReservedRegs(const MachineFunction &MF) const
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{
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BitVector Reserved(getNumRegs());
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Reserved.set(Teak::SP);
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Reserved.set(Teak::PC);
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Reserved.set(Teak::R7);
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Reserved.set(Teak::LC);
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//Reserved.set(Teak::SV);
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return Reserved;
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}
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const uint32_t* TeakRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
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CallingConv::ID) const {
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return CSR_RegMask;
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}
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const TargetRegisterClass* TeakRegisterInfo::getPointerRegClass(
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const MachineFunction &MF, unsigned Kind) const
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{
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if(Kind == 1)
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return &Teak::ABRegsRegClass;
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return &Teak::GRRegsRegClass;
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}
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bool TeakRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const
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{
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return true;
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}
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bool TeakRegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const
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{
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return true;
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}
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bool TeakRegisterInfo::useFPForScavengingIndex(const MachineFunction &MF) const
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{
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return false;
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}
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bool TeakRegisterInfo::requiresFrameIndexScavenging(const MachineFunction &MF) const
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{
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return false;//true;
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}
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bool TeakRegisterInfo::requiresVirtualBaseRegisters(const MachineFunction &MF) const
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{
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return false;//true;
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}
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unsigned TeakRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const
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{
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switch (RC->getID())
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{
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default:
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return 0;
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case Teak::GRRegsRegClassID:
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return 5;
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case Teak::SVRegRegClassID:
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return 0;
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case Teak::ABRegsRegClassID:
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return 4;
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case Teak::ALRegsRegClassID:
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return 2;
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case Teak::ABLRegsRegClassID:
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return 4;
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case Teak::RegNoBRegs16_nohRegClassID:
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return 9;
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}
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}
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void TeakRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
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int SPAdj, unsigned FIOperandNum,
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RegScavenger *RS) const {
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dbgs() << "eliminateFrameIndex\n";
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MachineInstr &MI = *II;
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const MachineFunction &MF = *MI.getParent()->getParent();
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const MachineFrameInfo& MFI = MF.getFrameInfo();
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MachineOperand &FIOp = MI.getOperand(FIOperandNum);
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unsigned FI = FIOp.getIndex();
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// Determine if we can eliminate the index from this kind of instruction.
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unsigned ImmOpIdx = 0;
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switch (MI.getOpcode()) {
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default:
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// Not supported yet.
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return;
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case Teak::STORE_REG_TO_STACK_PSEUDO_16:
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case Teak::STORE_REG_TO_STACK_PSEUDO_TRUNC16:
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case Teak::STORE_REG_TO_STACK_PSEUDO_32:
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case Teak::LOAD_REG_FROM_STACK_PSEUDO_16:
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case Teak::LOAD_REG_FROM_STACK_PSEUDO_16_SEXT40:
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case Teak::LOAD_REG_FROM_STACK_PSEUDO_16_ZEXT40:
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case Teak::LOAD_REG_FROM_STACK_PSEUDO_32_SEXT40:
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ImmOpIdx = FIOperandNum + 1;
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break;
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}
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// FIXME: check the size of offset.
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MachineOperand &ImmOp = MI.getOperand(ImmOpIdx);
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int Offset = MFI.getObjectOffset(FI) + MFI.getStackSize() + ImmOp.getImm();
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FIOp.ChangeToRegister(Teak::R7, false);
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ImmOp.setImm(-(Offset >> 1) - 1);
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}
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Register TeakRegisterInfo::getFrameRegister(const MachineFunction &MF) const
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{
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return Teak::R7;
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}
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bool TeakRegisterInfo::isFrameOffsetLegal(
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const MachineInstr* MI, unsigned BaseReg, int64_t Offset) const
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{
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dbgs() << "isFrameOffsetLegal\n";
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return true;//Offset == 0;
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}
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bool TeakRegisterInfo::needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const
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{
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return false;//Offset != 0;
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}
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int64_t TeakRegisterInfo::getFrameIndexInstrOffset(const MachineInstr* MI, int Idx) const
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{
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switch (MI->getOpcode())
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{
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default:
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return 0;
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case Teak::STORE_REG_TO_STACK_PSEUDO_16:
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case Teak::STORE_REG_TO_STACK_PSEUDO_TRUNC16:
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case Teak::STORE_REG_TO_STACK_PSEUDO_32:
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case Teak::LOAD_REG_FROM_STACK_PSEUDO_16:
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case Teak::LOAD_REG_FROM_STACK_PSEUDO_16_SEXT40:
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case Teak::LOAD_REG_FROM_STACK_PSEUDO_16_ZEXT40:
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case Teak::LOAD_REG_FROM_STACK_PSEUDO_32_SEXT40:
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return MI->getOperand(Idx + 1).getImm();
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}
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}
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void TeakRegisterInfo::materializeFrameBaseRegister(MachineBasicBlock *MBB,
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unsigned BaseReg, int FrameIdx, int64_t Offset) const
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{
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// dbgs() << "materializeFrameBaseRegister: " << BaseReg << "\n";
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// MachineBasicBlock::iterator Ins = MBB->begin();
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// DebugLoc DL; // Defaults to "unknown"
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// if (Ins != MBB->end())
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// DL = Ins->getDebugLoc();
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// const MachineFunction &MF = *MBB->getParent();
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// MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
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// const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
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// MRI.constrainRegClass(BaseReg, &Teak::FPRegClass);
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// BuildMI(*MBB, Ins, DL, get(Teak::ADDV_imm16_RegNoBRegs16), BaseReg)
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// .addImm(Offset)
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// .addReg(Teak::R7);
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}
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void TeakRegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, int64_t Offset) const
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{
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dbgs() << "resolveFrameIndex\n";
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MI.dump();
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const MachineFunction &MF = *MI.getParent()->getParent();
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const MachineFrameInfo& MFI = MF.getFrameInfo();
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MachineOperand* FIOp;
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//unsigned FI = FIOp.getIndex();
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// Determine if we can eliminate the index from this kind of instruction.
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unsigned ImmOpIdx = 0;
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switch (MI.getOpcode()) {
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default:
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// Not supported yet.
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return;
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case Teak::STORE_REG_TO_STACK_PSEUDO_16:
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case Teak::STORE_REG_TO_STACK_PSEUDO_TRUNC16:
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case Teak::STORE_REG_TO_STACK_PSEUDO_32:
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FIOp = &MI.getOperand(1);
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ImmOpIdx = 2;
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break;
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case Teak::LOAD_REG_FROM_STACK_PSEUDO_16:
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case Teak::LOAD_REG_FROM_STACK_PSEUDO_16_SEXT40:
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case Teak::LOAD_REG_FROM_STACK_PSEUDO_16_ZEXT40:
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case Teak::LOAD_REG_FROM_STACK_PSEUDO_32_SEXT40:
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FIOp = &MI.getOperand(1);
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ImmOpIdx = 2;
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break;
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}
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// FIXME: check the size of offset.
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MachineOperand &ImmOp = MI.getOperand(ImmOpIdx);
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FIOp->ChangeToRegister(BaseReg, false);
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ImmOp.setImm(Offset);
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}
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bool TeakRegisterInfo::shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg,
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const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC, LiveIntervals &LIS) const
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{
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dbgs() << "shouldCoalesce\n";
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MI->dump();
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dbgs() << "SrcRC: " << SrcRC->getID() << "\n";
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dbgs() << "SubReg: " << SubReg << "\n";
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dbgs() << "DstRC: " << DstRC->getID() << "\n";
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dbgs() << "DstSubReg: " << DstSubReg << "\n";
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dbgs() << "NewRC: " << NewRC->getID() << "\n";
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if (SrcRC->hasSuperClassEq(&Teak::SVRegRegClass) ||
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DstRC->hasSuperClassEq(&Teak::SVRegRegClass) ||
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NewRC->hasSuperClassEq(&Teak::SVRegRegClass))
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return false;
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if(DstSubReg == Teak::sub_16bit)
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return true;
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//if(SrcRC->hasSubClassEq(&Teak::GRRegsRegClass) && DstRC->hasSubClassEq(&Teak::GRRegsRegClass) && NewRC->hasSubClassEq(&Teak::GRRegsRegClass))
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// return true;
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if(SrcRC->hasSuperClassEq(&Teak::ABLRegsRegClass) && DstRC->hasSuperClassEq(&Teak::ABRegsRegClass) && NewRC->hasSuperClassEq(&Teak::ABRegsRegClass))
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return true;
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if(SrcRC->hasSuperClassEq(&Teak::ABRegsRegClass) && DstRC->hasSuperClassEq(&Teak::ABRegsRegClass) && NewRC->hasSuperClassEq(&Teak::ABRegsRegClass))
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return true;
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//return true;//false;
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if(SrcRC->hasSuperClassEq(&Teak::ARegsRegClass) && DstRC->hasSuperClassEq(&Teak::ARegsRegClass) && NewRC->hasSuperClassEq(&Teak::ARegsRegClass))
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return true;
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if(SrcRC->hasSuperClassEq(&Teak::ALRegsRegClass) && DstRC->hasSuperClassEq(&Teak::ALRegsRegClass) && NewRC->hasSuperClassEq(&Teak::ALRegsRegClass))
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return true;
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if (DstRC->hasSuperClassEq(&Teak::ALRegsRegClass) || NewRC->hasSuperClassEq(&Teak::ALRegsRegClass) ||
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DstRC->hasSuperClassEq(&Teak::ARegsRegClass) || NewRC->hasSuperClassEq(&Teak::ARegsRegClass))
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return false;
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return true;
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} |