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https://github.com/Gericom/teak-llvm.git
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be7a107070
This attempts to teach the cost model in Arm that code such as: %s = shl i32 %a, 3 %a = and i32 %s, %b Can under Arm or Thumb2 become: and r0, r1, r2, lsl #3 So the cost of the shift can essentially be free. To do this without trying to artificially adjust the cost of the "and" instruction, it needs to get the users of the shl and check if they are a type of instruction that the shift can be folded into. And so it needs to have access to the actual instruction in getArithmeticInstrCost, which if available is added as an extra parameter much like getCastInstrCost. We otherwise limit it to shifts with a single user, which should hopefully handle most of the cases. The list of instruction that the shift can be folded into include ADC, ADD, AND, BIC, CMP, EOR, MVN, ORR, ORN, RSB, SBC and SUB. This translates to Add, Sub, And, Or, Xor and ICmp. Differential Revision: https://reviews.llvm.org/D70966
74 lines
2.4 KiB
C++
74 lines
2.4 KiB
C++
//==- WebAssemblyTargetTransformInfo.h - WebAssembly-specific TTI -*- C++ -*-=//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// This file a TargetTransformInfo::Concept conforming object specific
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/// to the WebAssembly target machine.
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///
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/// It uses the target's detailed information to provide more precise answers to
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/// certain TTI queries, while letting the target independent and default TTI
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/// implementations handle the rest.
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///
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_WEBASSEMBLY_WEBASSEMBLYTARGETTRANSFORMINFO_H
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#define LLVM_LIB_TARGET_WEBASSEMBLY_WEBASSEMBLYTARGETTRANSFORMINFO_H
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#include "WebAssemblyTargetMachine.h"
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#include "llvm/CodeGen/BasicTTIImpl.h"
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#include <algorithm>
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namespace llvm {
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class WebAssemblyTTIImpl final : public BasicTTIImplBase<WebAssemblyTTIImpl> {
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typedef BasicTTIImplBase<WebAssemblyTTIImpl> BaseT;
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typedef TargetTransformInfo TTI;
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friend BaseT;
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const WebAssemblySubtarget *ST;
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const WebAssemblyTargetLowering *TLI;
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const WebAssemblySubtarget *getST() const { return ST; }
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const WebAssemblyTargetLowering *getTLI() const { return TLI; }
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public:
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WebAssemblyTTIImpl(const WebAssemblyTargetMachine *TM, const Function &F)
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: BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)),
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TLI(ST->getTargetLowering()) {}
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/// \name Scalar TTI Implementations
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/// @{
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// TODO: Implement more Scalar TTI for WebAssembly
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TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth) const;
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/// @}
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/// \name Vector TTI Implementations
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/// @{
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unsigned getNumberOfRegisters(unsigned ClassID) const;
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unsigned getRegisterBitWidth(bool Vector) const;
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unsigned getArithmeticInstrCost(
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unsigned Opcode, Type *Ty,
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TTI::OperandValueKind Opd1Info = TTI::OK_AnyValue,
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TTI::OperandValueKind Opd2Info = TTI::OK_AnyValue,
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TTI::OperandValueProperties Opd1PropInfo = TTI::OP_None,
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TTI::OperandValueProperties Opd2PropInfo = TTI::OP_None,
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ArrayRef<const Value *> Args = ArrayRef<const Value *>(),
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const Instruction *CxtI = nullptr);
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unsigned getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index);
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/// @}
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};
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} // end namespace llvm
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#endif
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