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0d0a1a53e3
Support for the QPX vector instruction set, used on the IBM BG/Q supercomputer, has recently been added to the LLVM PowerPC backend. This vector instruction set requires some ABI modifications because the ABI on the BG/Q expects <4 x double> vectors to be provided with 32-byte stack alignment, and to be handled as native vector types (similar to how Altivec vectors are handled on mainline PPC systems). I've named this ABI variant elfv1-qpx, have made this the default ABI when QPX is supported, and have updated the ABI handling code to provide QPX vectors with the correct stack alignment and associated register-assignment logic. llvm-svn: 231960
30 lines
1.0 KiB
C
30 lines
1.0 KiB
C
// RUN: %clang_cc1 -triple powerpc64-unknown-linux-gnu -emit-llvm -o - %s | FileCheck %s -check-prefix=ALL -check-prefix=NORMAL
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// RUN: %clang_cc1 -triple powerpc64-unknown-linux-gnu -emit-llvm -o - -target-abi elfv1-qpx %s | FileCheck %s -check-prefix=ALL -check-prefix=QPX
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typedef float v4sf __attribute__((vector_size(16)));
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typedef double v4df __attribute__((vector_size(32)));
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struct ssf { v4sf v; };
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struct sdf { v4df v; };
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struct ssf2 { v4sf v[2]; };
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struct sdf2 { v4df v[2]; };
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v4sf foo1(struct ssf a, v4sf b, struct ssf2 c) {
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return a.v + b;
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}
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// ALL-LABEL: define <4 x float> @foo1(<4 x float> inreg %a.coerce, <4 x float> %b, [2 x i128] %c.coerce)
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// ALL: ret <4 x float>
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v4df foo2(struct sdf a, v4df b, struct sdf2 c) {
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return a.v + b;
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}
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// QPX-LABEL: define <4 x double> @foo2(<4 x double> inreg %a.coerce, <4 x double> %b, [2 x i256] %c.coerce)
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// QPX: ret <4 x double>
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// NORMAL-LABEL: define void @foo2(<4 x double>* noalias sret %agg.result, [2 x i128] %a.coerce, <4 x double>*, [4 x i128] %c.coerce)
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// NORMAL: ret void
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