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https://github.com/Gericom/teak-llvm.git
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1f2b181689
intrin.h had forward declarations for these and lzcntintrin.h had implementations that were only available with -mlzcnt or a -march that supported the lzcnt feature. For MS compatibility we should always have these builtins available regardless of X86 being the target or the CPU support the lzcnt instruction. The backends should be able to gracefully fallback to something support even if its just shifts and bit ops. Unfortunately, gcc also implements 2 of the 3 function names here on X86 when lzcnt feature is enabled. This patch adds builtins for these for MSVC compatibility and drops the forward declarations from intrin.h. To keep the gcc compatibility the two intrinsics that collided have been turned into macros that use the X86 specific builtins with the lzcnt feature check. These macros are only defined when _MSC_VER is not defined. Without them being macros we can get a redefinition error because -ms-extensions doesn't seem to set _MSC_VER but does make the MS builtins available. Should fix PR40014 Differential Revision: https://reviews.llvm.org/D55677 llvm-svn: 349098
199 lines
8.2 KiB
C
199 lines
8.2 KiB
C
// RUN: %clang_cc1 -ffreestanding -fms-extensions \
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// RUN: -triple x86_64--darwin -Oz -emit-llvm %s -o - \
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// RUN: | FileCheck %s
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// RUN: %clang_cc1 -ffreestanding -fms-extensions \
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// RUN: -triple x86_64--linux -Oz -emit-llvm %s -o - \
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// RUN: | FileCheck %s
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// LP64 targets use 'long' as 'int' for MS intrinsics (-fms-extensions)
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#ifdef __LP64__
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#define LONG int
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#else
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#define LONG long
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#endif
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unsigned char test_BitScanForward(unsigned LONG *Index, unsigned LONG Mask) {
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return _BitScanForward(Index, Mask);
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}
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// CHECK: define{{.*}}i8 @test_BitScanForward(i32* {{[a-z_ ]*}}%Index, i32 {{[a-z_ ]*}}%Mask){{.*}}{
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// CHECK: [[ISNOTZERO:%[a-z0-9._]+]] = icmp eq i32 %Mask, 0
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// CHECK: br i1 [[ISNOTZERO]], label %[[END_LABEL:[a-z0-9._]+]], label %[[ISNOTZERO_LABEL:[a-z0-9._]+]]
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// CHECK: [[END_LABEL]]:
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// CHECK: [[RESULT:%[a-z0-9._]+]] = phi i8 [ 0, %[[ISZERO_LABEL:[a-z0-9._]+]] ], [ 1, %[[ISNOTZERO_LABEL]] ]
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// CHECK: ret i8 [[RESULT]]
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// CHECK: [[ISNOTZERO_LABEL]]:
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// CHECK: [[INDEX:%[0-9]+]] = tail call i32 @llvm.cttz.i32(i32 %Mask, i1 true)
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// CHECK: store i32 [[INDEX]], i32* %Index, align 4
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// CHECK: br label %[[END_LABEL]]
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unsigned char test_BitScanReverse(unsigned LONG *Index, unsigned LONG Mask) {
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return _BitScanReverse(Index, Mask);
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}
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// CHECK: define{{.*}}i8 @test_BitScanReverse(i32* {{[a-z_ ]*}}%Index, i32 {{[a-z_ ]*}}%Mask){{.*}}{
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// CHECK: [[ISNOTZERO:%[0-9]+]] = icmp eq i32 %Mask, 0
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// CHECK: br i1 [[ISNOTZERO]], label %[[END_LABEL:[a-z0-9._]+]], label %[[ISNOTZERO_LABEL:[a-z0-9._]+]]
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// CHECK: [[END_LABEL]]:
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// CHECK: [[RESULT:%[a-z0-9._]+]] = phi i8 [ 0, %[[ISZERO_LABEL:[a-z0-9._]+]] ], [ 1, %[[ISNOTZERO_LABEL]] ]
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// CHECK: ret i8 [[RESULT]]
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// CHECK: [[ISNOTZERO_LABEL]]:
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// CHECK: [[REVINDEX:%[0-9]+]] = tail call i32 @llvm.ctlz.i32(i32 %Mask, i1 true)
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// CHECK: [[INDEX:%[0-9]+]] = xor i32 [[REVINDEX]], 31
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// CHECK: store i32 [[INDEX]], i32* %Index, align 4
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// CHECK: br label %[[END_LABEL]]
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#if defined(__x86_64__)
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unsigned char test_BitScanForward64(unsigned LONG *Index, unsigned __int64 Mask) {
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return _BitScanForward64(Index, Mask);
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}
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// CHECK: define{{.*}}i8 @test_BitScanForward64(i32* {{[a-z_ ]*}}%Index, i64 {{[a-z_ ]*}}%Mask){{.*}}{
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// CHECK: [[ISNOTZERO:%[a-z0-9._]+]] = icmp eq i64 %Mask, 0
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// CHECK: br i1 [[ISNOTZERO]], label %[[END_LABEL:[a-z0-9._]+]], label %[[ISNOTZERO_LABEL:[a-z0-9._]+]]
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// CHECK: [[END_LABEL]]:
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// CHECK: [[RESULT:%[a-z0-9._]+]] = phi i8 [ 0, %[[ISZERO_LABEL:[a-z0-9._]+]] ], [ 1, %[[ISNOTZERO_LABEL]] ]
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// CHECK: ret i8 [[RESULT]]
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// CHECK: [[ISNOTZERO_LABEL]]:
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// CHECK: [[INDEX:%[0-9]+]] = tail call i64 @llvm.cttz.i64(i64 %Mask, i1 true)
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// CHECK: [[TRUNC_INDEX:%[0-9]+]] = trunc i64 [[INDEX]] to i32
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// CHECK: store i32 [[TRUNC_INDEX]], i32* %Index, align 4
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// CHECK: br label %[[END_LABEL]]
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unsigned char test_BitScanReverse64(unsigned LONG *Index, unsigned __int64 Mask) {
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return _BitScanReverse64(Index, Mask);
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}
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// CHECK: define{{.*}}i8 @test_BitScanReverse64(i32* {{[a-z_ ]*}}%Index, i64 {{[a-z_ ]*}}%Mask){{.*}}{
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// CHECK: [[ISNOTZERO:%[0-9]+]] = icmp eq i64 %Mask, 0
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// CHECK: br i1 [[ISNOTZERO]], label %[[END_LABEL:[a-z0-9._]+]], label %[[ISNOTZERO_LABEL:[a-z0-9._]+]]
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// CHECK: [[END_LABEL]]:
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// CHECK: [[RESULT:%[a-z0-9._]+]] = phi i8 [ 0, %[[ISZERO_LABEL:[a-z0-9._]+]] ], [ 1, %[[ISNOTZERO_LABEL]] ]
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// CHECK: ret i8 [[RESULT]]
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// CHECK: [[ISNOTZERO_LABEL]]:
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// CHECK: [[REVINDEX:%[0-9]+]] = tail call i64 @llvm.ctlz.i64(i64 %Mask, i1 true)
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// CHECK: [[TRUNC_REVINDEX:%[0-9]+]] = trunc i64 [[REVINDEX]] to i32
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// CHECK: [[INDEX:%[0-9]+]] = xor i32 [[TRUNC_REVINDEX]], 63
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// CHECK: store i32 [[INDEX]], i32* %Index, align 4
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// CHECK: br label %[[END_LABEL]]
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#endif
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LONG test_InterlockedExchange(LONG volatile *value, LONG mask) {
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return _InterlockedExchange(value, mask);
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}
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// CHECK: define{{.*}}i32 @test_InterlockedExchange(i32*{{[a-z_ ]*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{
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// CHECK: [[RESULT:%[0-9]+]] = atomicrmw xchg i32* %value, i32 %mask seq_cst
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// CHECK: ret i32 [[RESULT:%[0-9]+]]
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// CHECK: }
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LONG test_InterlockedExchangeAdd(LONG volatile *value, LONG mask) {
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return _InterlockedExchangeAdd(value, mask);
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}
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// CHECK: define{{.*}}i32 @test_InterlockedExchangeAdd(i32*{{[a-z_ ]*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{
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// CHECK: [[RESULT:%[0-9]+]] = atomicrmw add i32* %value, i32 %mask seq_cst
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// CHECK: ret i32 [[RESULT:%[0-9]+]]
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// CHECK: }
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LONG test_InterlockedExchangeSub(LONG volatile *value, LONG mask) {
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return _InterlockedExchangeSub(value, mask);
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}
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// CHECK: define{{.*}}i32 @test_InterlockedExchangeSub(i32*{{[a-z_ ]*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{
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// CHECK: [[RESULT:%[0-9]+]] = atomicrmw sub i32* %value, i32 %mask seq_cst
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// CHECK: ret i32 [[RESULT:%[0-9]+]]
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// CHECK: }
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LONG test_InterlockedOr(LONG volatile *value, LONG mask) {
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return _InterlockedOr(value, mask);
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}
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// CHECK: define{{.*}}i32 @test_InterlockedOr(i32*{{[a-z_ ]*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{
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// CHECK: [[RESULT:%[0-9]+]] = atomicrmw or i32* %value, i32 %mask seq_cst
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// CHECK: ret i32 [[RESULT:%[0-9]+]]
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// CHECK: }
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LONG test_InterlockedXor(LONG volatile *value, LONG mask) {
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return _InterlockedXor(value, mask);
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}
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// CHECK: define{{.*}}i32 @test_InterlockedXor(i32*{{[a-z_ ]*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{
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// CHECK: [[RESULT:%[0-9]+]] = atomicrmw xor i32* %value, i32 %mask seq_cst
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// CHECK: ret i32 [[RESULT:%[0-9]+]]
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// CHECK: }
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LONG test_InterlockedAnd(LONG volatile *value, LONG mask) {
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return _InterlockedAnd(value, mask);
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}
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// CHECK: define{{.*}}i32 @test_InterlockedAnd(i32*{{[a-z_ ]*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{
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// CHECK: [[RESULT:%[0-9]+]] = atomicrmw and i32* %value, i32 %mask seq_cst
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// CHECK: ret i32 [[RESULT:%[0-9]+]]
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// CHECK: }
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LONG test_InterlockedCompareExchange(LONG volatile *Destination, LONG Exchange, LONG Comperand) {
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return _InterlockedCompareExchange(Destination, Exchange, Comperand);
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}
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// CHECK: define{{.*}}i32 @test_InterlockedCompareExchange(i32*{{[a-z_ ]*}}%Destination, i32{{[a-z_ ]*}}%Exchange, i32{{[a-z_ ]*}}%Comperand){{.*}}{
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// CHECK: [[TMP:%[0-9]+]] = cmpxchg volatile i32* %Destination, i32 %Comperand, i32 %Exchange seq_cst seq_cst
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// CHECK: [[RESULT:%[0-9]+]] = extractvalue { i32, i1 } [[TMP]], 0
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// CHECK: ret i32 [[RESULT]]
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// CHECK: }
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LONG test_InterlockedIncrement(LONG volatile *Addend) {
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return _InterlockedIncrement(Addend);
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}
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// CHECK: define{{.*}}i32 @test_InterlockedIncrement(i32*{{[a-z_ ]*}}%Addend){{.*}}{
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// CHECK: [[TMP:%[0-9]+]] = atomicrmw add i32* %Addend, i32 1 seq_cst
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// CHECK: [[RESULT:%[0-9]+]] = add i32 [[TMP]], 1
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// CHECK: ret i32 [[RESULT]]
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// CHECK: }
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LONG test_InterlockedDecrement(LONG volatile *Addend) {
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return _InterlockedDecrement(Addend);
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}
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// CHECK: define{{.*}}i32 @test_InterlockedDecrement(i32*{{[a-z_ ]*}}%Addend){{.*}}{
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// CHECK: [[TMP:%[0-9]+]] = atomicrmw sub i32* %Addend, i32 1 seq_cst
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// CHECK: [[RESULT:%[0-9]+]] = add i32 [[TMP]], -1
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// CHECK: ret i32 [[RESULT]]
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// CHECK: }
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unsigned short test__lzcnt16(unsigned short x) {
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return __lzcnt16(x);
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}
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// CHECK: i16 @test__lzcnt16
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// CHECK: [[RESULT:%[0-9]+]] = tail call i16 @llvm.ctlz.i16(i16 %x, i1 false)
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// CHECK: ret i16 [[RESULT]]
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// CHECK: }
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unsigned int test__lzcnt(unsigned int x) {
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return __lzcnt(x);
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}
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// CHECK: i32 @test__lzcnt
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// CHECK: [[RESULT:%[0-9]+]] = tail call i32 @llvm.ctlz.i32(i32 %x, i1 false)
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// CHECK: ret i32 [[RESULT]]
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// CHECK: }
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unsigned __int64 test__lzcnt64(unsigned __int64 x) {
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return __lzcnt64(x);
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}
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// CHECK: i64 @test__lzcnt64
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// CHECK: [[RESULT:%[0-9]+]] = tail call i64 @llvm.ctlz.i64(i64 %x, i1 false)
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// CHECK: ret i64 [[RESULT]]
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// CHECK: }
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unsigned short test__popcnt16(unsigned short x) {
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return __popcnt16(x);
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}
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// CHECK: i16 @test__popcnt16
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// CHECK: [[RESULT:%[0-9]+]] = tail call i16 @llvm.ctpop.i16(i16 %x)
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// CHECK: ret i16 [[RESULT]]
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// CHECK: }
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unsigned int test__popcnt(unsigned int x) {
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return __popcnt(x);
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}
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// CHECK: i32 @test__popcnt
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// CHECK: [[RESULT:%[0-9]+]] = tail call i32 @llvm.ctpop.i32(i32 %x)
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// CHECK: ret i32 [[RESULT]]
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// CHECK: }
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unsigned __int64 test__popcnt64(unsigned __int64 x) {
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return __popcnt64(x);
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}
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// CHECK: i64 @test__popcnt64
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// CHECK: [[RESULT:%[0-9]+]] = tail call i64 @llvm.ctpop.i64(i64 %x)
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// CHECK: ret i64 [[RESULT]]
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// CHECK: }
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