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https://github.com/Gericom/teak-llvm.git
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9769debf88
Summary: Use the SP32 physical register as the base for FrameIndex lowering. Update it and the __stack_pointer global var in the prolog and epilog. Extend the mapping of virtual registers to wasm locals to include the physical registers. Rather than modify the target-independent PrologEpilogInserter (which asserts that there are no virtual registers left) include a slightly-modified copy for Wasm that does not have this assertion and only clears the virtual registers if scavenging was needed (which of course it isn't for wasm). Differential Revision: http://reviews.llvm.org/D15344 llvm-svn: 255392
87 lines
2.7 KiB
C++
87 lines
2.7 KiB
C++
//===-- WebAssemblyPeephole.cpp - WebAssembly Peephole Optimiztions -------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// \brief Late peephole optimizations for WebAssembly.
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///
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//===----------------------------------------------------------------------===//
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#include "WebAssembly.h"
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#include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
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#include "WebAssemblyMachineFunctionInfo.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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using namespace llvm;
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#define DEBUG_TYPE "wasm-peephole"
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namespace {
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class WebAssemblyPeephole final : public MachineFunctionPass {
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const char *getPassName() const override {
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return "WebAssembly late peephole optimizer";
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}
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.setPreservesCFG();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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public:
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static char ID;
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WebAssemblyPeephole() : MachineFunctionPass(ID) {}
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};
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} // end anonymous namespace
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char WebAssemblyPeephole::ID = 0;
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FunctionPass *llvm::createWebAssemblyPeephole() {
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return new WebAssemblyPeephole();
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}
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bool WebAssemblyPeephole::runOnMachineFunction(MachineFunction &MF) {
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bool Changed = false;
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MachineRegisterInfo &MRI = MF.getRegInfo();
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WebAssemblyFunctionInfo &MFI = *MF.getInfo<WebAssemblyFunctionInfo>();
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for (auto &MBB : MF)
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for (auto &MI : MBB)
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switch (MI.getOpcode()) {
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default:
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break;
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case WebAssembly::STORE8_I32:
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case WebAssembly::STORE16_I32:
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case WebAssembly::STORE8_I64:
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case WebAssembly::STORE16_I64:
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case WebAssembly::STORE32_I64:
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case WebAssembly::STORE_F32:
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case WebAssembly::STORE_F64:
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case WebAssembly::STORE_I32:
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case WebAssembly::STORE_I64: {
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// Store instructions return their value operand. If we ended up using
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// the same register for both, replace it with a dead def so that it
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// can use $discard instead.
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MachineOperand &MO = MI.getOperand(0);
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unsigned OldReg = MO.getReg();
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// TODO: Handle SP/physregs
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if (OldReg == MI.getOperand(3).getReg()
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&& TargetRegisterInfo::isVirtualRegister(MI.getOperand(3).getReg())) {
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Changed = true;
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unsigned NewReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg));
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MO.setReg(NewReg);
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MO.setIsDead();
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MFI.stackifyVReg(NewReg);
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MFI.addWAReg(NewReg, WebAssemblyFunctionInfo::UnusedReg);
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}
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}
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}
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return Changed;
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}
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