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https://github.com/Gericom/teak-llvm.git
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a1bc0f5662
This patch re-introduces the MCContext member that was removed from MCDisassembler in r206063, and requires that an MCContext be passed in at MCDisassembler construction time. (Previously the MCContext member had been initialized in an ad-hoc fashion after construction). The MCCContext member can be used by MCDisassembler sub-classes to construct constant or target-specific MCExprs. This patch updates disassemblers for in-tree targets, and provides the MCRegisterInfo instance that some disassemblers were using through the MCContext (previously those backends were constructing their own MCRegisterInfo instances). llvm-svn: 206241
481 lines
16 KiB
C++
481 lines
16 KiB
C++
//===- SparcDisassembler.cpp - Disassembler for Sparc -----------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file is part of the Sparc Disassembler.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "sparc-disassembler"
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#include "Sparc.h"
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#include "SparcRegisterInfo.h"
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#include "SparcSubtarget.h"
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#include "llvm/MC/MCDisassembler.h"
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#include "llvm/MC/MCFixedLenDisassembler.h"
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#include "llvm/Support/MemoryObject.h"
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#include "llvm/Support/TargetRegistry.h"
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using namespace llvm;
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typedef MCDisassembler::DecodeStatus DecodeStatus;
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namespace {
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/// SparcDisassembler - a disassembler class for Sparc.
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class SparcDisassembler : public MCDisassembler {
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public:
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/// Constructor - Initializes the disassembler.
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///
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SparcDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
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MCDisassembler(STI, Ctx)
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{}
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virtual ~SparcDisassembler() {}
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/// getInstruction - See MCDisassembler.
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virtual DecodeStatus getInstruction(MCInst &instr,
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uint64_t &size,
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const MemoryObject ®ion,
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uint64_t address,
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raw_ostream &vStream,
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raw_ostream &cStream) const;
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};
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}
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namespace llvm {
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extern Target TheSparcTarget, TheSparcV9Target;
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}
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static MCDisassembler *createSparcDisassembler(
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const Target &T,
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const MCSubtargetInfo &STI,
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MCContext &Ctx) {
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return new SparcDisassembler(STI, Ctx);
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}
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extern "C" void LLVMInitializeSparcDisassembler() {
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// Register the disassembler.
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TargetRegistry::RegisterMCDisassembler(TheSparcTarget,
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createSparcDisassembler);
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TargetRegistry::RegisterMCDisassembler(TheSparcV9Target,
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createSparcDisassembler);
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}
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static const unsigned IntRegDecoderTable[] = {
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SP::G0, SP::G1, SP::G2, SP::G3,
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SP::G4, SP::G5, SP::G6, SP::G7,
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SP::O0, SP::O1, SP::O2, SP::O3,
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SP::O4, SP::O5, SP::O6, SP::O7,
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SP::L0, SP::L1, SP::L2, SP::L3,
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SP::L4, SP::L5, SP::L6, SP::L7,
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SP::I0, SP::I1, SP::I2, SP::I3,
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SP::I4, SP::I5, SP::I6, SP::I7 };
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static const unsigned FPRegDecoderTable[] = {
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SP::F0, SP::F1, SP::F2, SP::F3,
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SP::F4, SP::F5, SP::F6, SP::F7,
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SP::F8, SP::F9, SP::F10, SP::F11,
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SP::F12, SP::F13, SP::F14, SP::F15,
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SP::F16, SP::F17, SP::F18, SP::F19,
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SP::F20, SP::F21, SP::F22, SP::F23,
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SP::F24, SP::F25, SP::F26, SP::F27,
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SP::F28, SP::F29, SP::F30, SP::F31 };
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static const unsigned DFPRegDecoderTable[] = {
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SP::D0, SP::D16, SP::D1, SP::D17,
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SP::D2, SP::D18, SP::D3, SP::D19,
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SP::D4, SP::D20, SP::D5, SP::D21,
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SP::D6, SP::D22, SP::D7, SP::D23,
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SP::D8, SP::D24, SP::D9, SP::D25,
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SP::D10, SP::D26, SP::D11, SP::D27,
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SP::D12, SP::D28, SP::D13, SP::D29,
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SP::D14, SP::D30, SP::D15, SP::D31 };
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static const unsigned QFPRegDecoderTable[] = {
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SP::Q0, SP::Q8, ~0U, ~0U,
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SP::Q1, SP::Q9, ~0U, ~0U,
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SP::Q2, SP::Q10, ~0U, ~0U,
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SP::Q3, SP::Q11, ~0U, ~0U,
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SP::Q4, SP::Q12, ~0U, ~0U,
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SP::Q5, SP::Q13, ~0U, ~0U,
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SP::Q6, SP::Q14, ~0U, ~0U,
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SP::Q7, SP::Q15, ~0U, ~0U } ;
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static const unsigned FCCRegDecoderTable[] = {
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SP::FCC0, SP::FCC1, SP::FCC2, SP::FCC3 };
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static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder) {
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if (RegNo > 31)
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return MCDisassembler::Fail;
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unsigned Reg = IntRegDecoderTable[RegNo];
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Inst.addOperand(MCOperand::CreateReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeI64RegsRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder) {
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if (RegNo > 31)
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return MCDisassembler::Fail;
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unsigned Reg = IntRegDecoderTable[RegNo];
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Inst.addOperand(MCOperand::CreateReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeFPRegsRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder) {
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if (RegNo > 31)
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return MCDisassembler::Fail;
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unsigned Reg = FPRegDecoderTable[RegNo];
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Inst.addOperand(MCOperand::CreateReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeDFPRegsRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder) {
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if (RegNo > 31)
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return MCDisassembler::Fail;
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unsigned Reg = DFPRegDecoderTable[RegNo];
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Inst.addOperand(MCOperand::CreateReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeQFPRegsRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder) {
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if (RegNo > 31)
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return MCDisassembler::Fail;
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unsigned Reg = QFPRegDecoderTable[RegNo];
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if (Reg == ~0U)
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return MCDisassembler::Fail;
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Inst.addOperand(MCOperand::CreateReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeFCCRegsRegisterClass(MCInst &Inst, unsigned RegNo,
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uint64_t Address,
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const void *Decoder) {
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if (RegNo > 3)
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return MCDisassembler::Fail;
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Inst.addOperand(MCOperand::CreateReg(FCCRegDecoderTable[RegNo]));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeLoadInt(MCInst &Inst, unsigned insn, uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeLoadFP(MCInst &Inst, unsigned insn, uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeLoadDFP(MCInst &Inst, unsigned insn, uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeLoadQFP(MCInst &Inst, unsigned insn, uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeStoreInt(MCInst &Inst, unsigned insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeStoreFP(MCInst &Inst, unsigned insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeStoreDFP(MCInst &Inst, unsigned insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeStoreQFP(MCInst &Inst, unsigned insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeCall(MCInst &Inst, unsigned insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeSIMM13(MCInst &Inst, unsigned insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeJMPL(MCInst &Inst, unsigned insn, uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeReturn(MCInst &MI, unsigned insn, uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeSWAP(MCInst &Inst, unsigned insn, uint64_t Address,
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const void *Decoder);
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#include "SparcGenDisassemblerTables.inc"
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/// readInstruction - read four bytes from the MemoryObject
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/// and return 32 bit word.
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static DecodeStatus readInstruction32(const MemoryObject ®ion,
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uint64_t address,
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uint64_t &size,
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uint32_t &insn) {
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uint8_t Bytes[4];
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// We want to read exactly 4 Bytes of data.
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if (region.readBytes(address, 4, Bytes) == -1) {
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size = 0;
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return MCDisassembler::Fail;
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}
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// Encoded as a big-endian 32-bit word in the stream.
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insn = (Bytes[3] << 0) |
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(Bytes[2] << 8) |
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(Bytes[1] << 16) |
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(Bytes[0] << 24);
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return MCDisassembler::Success;
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}
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DecodeStatus
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SparcDisassembler::getInstruction(MCInst &instr,
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uint64_t &Size,
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const MemoryObject &Region,
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uint64_t Address,
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raw_ostream &vStream,
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raw_ostream &cStream) const {
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uint32_t Insn;
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DecodeStatus Result = readInstruction32(Region, Address, Size, Insn);
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if (Result == MCDisassembler::Fail)
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return MCDisassembler::Fail;
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// Calling the auto-generated decoder function.
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Result = decodeInstruction(DecoderTableSparc32, instr, Insn, Address,
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this, STI);
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if (Result != MCDisassembler::Fail) {
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Size = 4;
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return Result;
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}
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return MCDisassembler::Fail;
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}
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typedef DecodeStatus (*DecodeFunc)(MCInst &MI, unsigned insn, uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeMem(MCInst &MI, unsigned insn, uint64_t Address,
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const void *Decoder,
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bool isLoad, DecodeFunc DecodeRD) {
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unsigned rd = fieldFromInstruction(insn, 25, 5);
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unsigned rs1 = fieldFromInstruction(insn, 14, 5);
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bool isImm = fieldFromInstruction(insn, 13, 1);
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unsigned rs2 = 0;
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unsigned simm13 = 0;
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if (isImm)
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simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
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else
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rs2 = fieldFromInstruction(insn, 0, 5);
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DecodeStatus status;
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if (isLoad) {
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status = DecodeRD(MI, rd, Address, Decoder);
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if (status != MCDisassembler::Success)
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return status;
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}
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// Decode rs1.
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status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
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if (status != MCDisassembler::Success)
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return status;
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// Decode imm|rs2.
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if (isImm)
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MI.addOperand(MCOperand::CreateImm(simm13));
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else {
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status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
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if (status != MCDisassembler::Success)
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return status;
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}
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if (!isLoad) {
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status = DecodeRD(MI, rd, Address, Decoder);
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if (status != MCDisassembler::Success)
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return status;
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}
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeLoadInt(MCInst &Inst, unsigned insn, uint64_t Address,
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const void *Decoder) {
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return DecodeMem(Inst, insn, Address, Decoder, true,
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DecodeIntRegsRegisterClass);
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}
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static DecodeStatus DecodeLoadFP(MCInst &Inst, unsigned insn, uint64_t Address,
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const void *Decoder) {
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return DecodeMem(Inst, insn, Address, Decoder, true,
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DecodeFPRegsRegisterClass);
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}
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static DecodeStatus DecodeLoadDFP(MCInst &Inst, unsigned insn, uint64_t Address,
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const void *Decoder) {
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return DecodeMem(Inst, insn, Address, Decoder, true,
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DecodeDFPRegsRegisterClass);
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}
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static DecodeStatus DecodeLoadQFP(MCInst &Inst, unsigned insn, uint64_t Address,
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const void *Decoder) {
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return DecodeMem(Inst, insn, Address, Decoder, true,
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DecodeQFPRegsRegisterClass);
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}
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static DecodeStatus DecodeStoreInt(MCInst &Inst, unsigned insn,
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uint64_t Address, const void *Decoder) {
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return DecodeMem(Inst, insn, Address, Decoder, false,
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DecodeIntRegsRegisterClass);
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}
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static DecodeStatus DecodeStoreFP(MCInst &Inst, unsigned insn, uint64_t Address,
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const void *Decoder) {
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return DecodeMem(Inst, insn, Address, Decoder, false,
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DecodeFPRegsRegisterClass);
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}
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static DecodeStatus DecodeStoreDFP(MCInst &Inst, unsigned insn,
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uint64_t Address, const void *Decoder) {
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return DecodeMem(Inst, insn, Address, Decoder, false,
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DecodeDFPRegsRegisterClass);
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}
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static DecodeStatus DecodeStoreQFP(MCInst &Inst, unsigned insn,
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uint64_t Address, const void *Decoder) {
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return DecodeMem(Inst, insn, Address, Decoder, false,
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DecodeQFPRegsRegisterClass);
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}
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static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch,
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uint64_t Address, uint64_t Offset,
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uint64_t Width, MCInst &MI,
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const void *Decoder) {
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const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
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return Dis->tryAddingSymbolicOperand(MI, Value, Address, isBranch,
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Offset, Width);
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}
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static DecodeStatus DecodeCall(MCInst &MI, unsigned insn,
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uint64_t Address, const void *Decoder) {
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unsigned tgt = fieldFromInstruction(insn, 0, 30);
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tgt <<= 2;
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if (!tryAddingSymbolicOperand(tgt+Address, false, Address,
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0, 30, MI, Decoder))
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MI.addOperand(MCOperand::CreateImm(tgt));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeSIMM13(MCInst &MI, unsigned insn,
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uint64_t Address, const void *Decoder) {
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unsigned tgt = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
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MI.addOperand(MCOperand::CreateImm(tgt));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeJMPL(MCInst &MI, unsigned insn, uint64_t Address,
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const void *Decoder) {
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unsigned rd = fieldFromInstruction(insn, 25, 5);
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unsigned rs1 = fieldFromInstruction(insn, 14, 5);
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unsigned isImm = fieldFromInstruction(insn, 13, 1);
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unsigned rs2 = 0;
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unsigned simm13 = 0;
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if (isImm)
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simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
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else
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rs2 = fieldFromInstruction(insn, 0, 5);
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// Decode RD.
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DecodeStatus status = DecodeIntRegsRegisterClass(MI, rd, Address, Decoder);
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if (status != MCDisassembler::Success)
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return status;
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// Decode RS1.
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status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
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if (status != MCDisassembler::Success)
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return status;
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// Decode RS1 | SIMM13.
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if (isImm)
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MI.addOperand(MCOperand::CreateImm(simm13));
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else {
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status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
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if (status != MCDisassembler::Success)
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return status;
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}
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeReturn(MCInst &MI, unsigned insn, uint64_t Address,
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const void *Decoder) {
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unsigned rs1 = fieldFromInstruction(insn, 14, 5);
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unsigned isImm = fieldFromInstruction(insn, 13, 1);
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unsigned rs2 = 0;
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unsigned simm13 = 0;
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if (isImm)
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simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
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else
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rs2 = fieldFromInstruction(insn, 0, 5);
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// Decode RS1.
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DecodeStatus status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
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if (status != MCDisassembler::Success)
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return status;
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// Decode RS2 | SIMM13.
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if (isImm)
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MI.addOperand(MCOperand::CreateImm(simm13));
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else {
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status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
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if (status != MCDisassembler::Success)
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return status;
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}
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeSWAP(MCInst &MI, unsigned insn, uint64_t Address,
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const void *Decoder) {
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unsigned rd = fieldFromInstruction(insn, 25, 5);
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unsigned rs1 = fieldFromInstruction(insn, 14, 5);
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unsigned isImm = fieldFromInstruction(insn, 13, 1);
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unsigned rs2 = 0;
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unsigned simm13 = 0;
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if (isImm)
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simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
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else
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rs2 = fieldFromInstruction(insn, 0, 5);
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// Decode RD.
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DecodeStatus status = DecodeIntRegsRegisterClass(MI, rd, Address, Decoder);
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if (status != MCDisassembler::Success)
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return status;
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// Decode RS1.
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status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
|
|
if (status != MCDisassembler::Success)
|
|
return status;
|
|
|
|
// Decode RS1 | SIMM13.
|
|
if (isImm)
|
|
MI.addOperand(MCOperand::CreateImm(simm13));
|
|
else {
|
|
status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
|
|
if (status != MCDisassembler::Success)
|
|
return status;
|
|
}
|
|
return MCDisassembler::Success;
|
|
}
|