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9d3f12501a
%lo(), %hi(), and %pcrel_hi() are supported and test cases have been added to ensure the appropriate fixups and relocations are generated. I've added an instruction format field which is used in RISCVMCCodeEmitter to, for instance, tell whether it should emit a lo12_i fixup or a lo12_s fixup (RISC-V has two 12-bit immediate encodings depending on the instruction type). Differential Revision: https://reviews.llvm.org/D23568 llvm-svn: 314389
69 lines
2.3 KiB
C++
69 lines
2.3 KiB
C++
//===-- RISCVELFObjectWriter.cpp - RISCV ELF Writer -----------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/RISCVFixupKinds.h"
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#include "MCTargetDesc/RISCVMCTargetDesc.h"
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#include "llvm/MC/MCELFObjectWriter.h"
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#include "llvm/MC/MCFixup.h"
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#include "llvm/Support/ErrorHandling.h"
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using namespace llvm;
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namespace {
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class RISCVELFObjectWriter : public MCELFObjectTargetWriter {
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public:
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RISCVELFObjectWriter(uint8_t OSABI, bool Is64Bit);
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~RISCVELFObjectWriter() override;
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protected:
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unsigned getRelocType(MCContext &Ctx, const MCValue &Target,
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const MCFixup &Fixup, bool IsPCRel) const override;
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};
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}
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RISCVELFObjectWriter::RISCVELFObjectWriter(uint8_t OSABI, bool Is64Bit)
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: MCELFObjectTargetWriter(Is64Bit, OSABI, ELF::EM_RISCV,
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/*HasRelocationAddend*/ true) {}
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RISCVELFObjectWriter::~RISCVELFObjectWriter() {}
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unsigned RISCVELFObjectWriter::getRelocType(MCContext &Ctx,
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const MCValue &Target,
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const MCFixup &Fixup,
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bool IsPCRel) const {
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// Determine the type of the relocation
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switch ((unsigned)Fixup.getKind()) {
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default:
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llvm_unreachable("invalid fixup kind!");
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case FK_Data_4:
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return ELF::R_RISCV_32;
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case FK_Data_8:
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return ELF::R_RISCV_64;
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case RISCV::fixup_riscv_hi20:
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return ELF::R_RISCV_HI20;
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case RISCV::fixup_riscv_lo12_i:
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return ELF::R_RISCV_LO12_I;
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case RISCV::fixup_riscv_lo12_s:
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return ELF::R_RISCV_LO12_S;
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case RISCV::fixup_riscv_pcrel_hi20:
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return ELF::R_RISCV_PCREL_HI20;
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case RISCV::fixup_riscv_jal:
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return ELF::R_RISCV_JAL;
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case RISCV::fixup_riscv_branch:
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return ELF::R_RISCV_BRANCH;
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}
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}
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MCObjectWriter *llvm::createRISCVELFObjectWriter(raw_pwrite_stream &OS,
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uint8_t OSABI, bool Is64Bit) {
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MCELFObjectTargetWriter *MOTW = new RISCVELFObjectWriter(OSABI, Is64Bit);
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return createELFObjectWriter(MOTW, OS, /*IsLittleEndian*/ true);
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}
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