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to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
102 lines
3.7 KiB
C++
102 lines
3.7 KiB
C++
//===-- RISCVMCTargetDesc.cpp - RISCV Target Descriptions -----------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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///
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/// This file provides RISCV-specific target descriptions.
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///
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//===----------------------------------------------------------------------===//
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#include "RISCVMCTargetDesc.h"
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#include "InstPrinter/RISCVInstPrinter.h"
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#include "RISCVELFStreamer.h"
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#include "RISCVMCAsmInfo.h"
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#include "RISCVTargetStreamer.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/TargetRegistry.h"
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#define GET_INSTRINFO_MC_DESC
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#include "RISCVGenInstrInfo.inc"
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#define GET_REGINFO_MC_DESC
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#include "RISCVGenRegisterInfo.inc"
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#define GET_SUBTARGETINFO_MC_DESC
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#include "RISCVGenSubtargetInfo.inc"
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using namespace llvm;
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static MCInstrInfo *createRISCVMCInstrInfo() {
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MCInstrInfo *X = new MCInstrInfo();
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InitRISCVMCInstrInfo(X);
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return X;
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}
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static MCRegisterInfo *createRISCVMCRegisterInfo(const Triple &TT) {
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MCRegisterInfo *X = new MCRegisterInfo();
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InitRISCVMCRegisterInfo(X, RISCV::X1);
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return X;
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}
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static MCAsmInfo *createRISCVMCAsmInfo(const MCRegisterInfo &MRI,
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const Triple &TT) {
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return new RISCVMCAsmInfo(TT);
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}
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static MCSubtargetInfo *createRISCVMCSubtargetInfo(const Triple &TT,
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StringRef CPU, StringRef FS) {
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std::string CPUName = CPU;
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if (CPUName.empty())
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CPUName = TT.isArch64Bit() ? "generic-rv64" : "generic-rv32";
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return createRISCVMCSubtargetInfoImpl(TT, CPUName, FS);
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}
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static MCInstPrinter *createRISCVMCInstPrinter(const Triple &T,
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unsigned SyntaxVariant,
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const MCAsmInfo &MAI,
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const MCInstrInfo &MII,
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const MCRegisterInfo &MRI) {
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return new RISCVInstPrinter(MAI, MII, MRI);
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}
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static MCTargetStreamer *
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createRISCVObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) {
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const Triple &TT = STI.getTargetTriple();
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if (TT.isOSBinFormatELF())
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return new RISCVTargetELFStreamer(S, STI);
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return nullptr;
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}
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static MCTargetStreamer *createRISCVAsmTargetStreamer(MCStreamer &S,
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formatted_raw_ostream &OS,
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MCInstPrinter *InstPrint,
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bool isVerboseAsm) {
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return new RISCVTargetAsmStreamer(S, OS);
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}
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extern "C" void LLVMInitializeRISCVTargetMC() {
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for (Target *T : {&getTheRISCV32Target(), &getTheRISCV64Target()}) {
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TargetRegistry::RegisterMCAsmInfo(*T, createRISCVMCAsmInfo);
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TargetRegistry::RegisterMCInstrInfo(*T, createRISCVMCInstrInfo);
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TargetRegistry::RegisterMCRegInfo(*T, createRISCVMCRegisterInfo);
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TargetRegistry::RegisterMCAsmBackend(*T, createRISCVAsmBackend);
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TargetRegistry::RegisterMCCodeEmitter(*T, createRISCVMCCodeEmitter);
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TargetRegistry::RegisterMCInstPrinter(*T, createRISCVMCInstPrinter);
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TargetRegistry::RegisterMCSubtargetInfo(*T, createRISCVMCSubtargetInfo);
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TargetRegistry::RegisterObjectTargetStreamer(
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*T, createRISCVObjectTargetStreamer);
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// Register the asm target streamer.
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TargetRegistry::RegisterAsmTargetStreamer(*T, createRISCVAsmTargetStreamer);
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}
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}
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