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288 lines
8.2 KiB
C++
288 lines
8.2 KiB
C++
//===-- MipsInstPrinter.cpp - Convert Mips MCInst to assembly syntax ------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This class prints an Mips MCInst to a .s file.
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//
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//===----------------------------------------------------------------------===//
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#include "MipsInstPrinter.h"
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#include "MCTargetDesc/MipsMCExpr.h"
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#include "MipsInstrInfo.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCSymbol.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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#define DEBUG_TYPE "asm-printer"
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#define PRINT_ALIAS_INSTR
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#include "MipsGenAsmWriter.inc"
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template<unsigned R>
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static bool isReg(const MCInst &MI, unsigned OpNo) {
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assert(MI.getOperand(OpNo).isReg() && "Register operand expected.");
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return MI.getOperand(OpNo).getReg() == R;
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}
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const char* Mips::MipsFCCToString(Mips::CondCode CC) {
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switch (CC) {
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case FCOND_F:
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case FCOND_T: return "f";
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case FCOND_UN:
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case FCOND_OR: return "un";
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case FCOND_OEQ:
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case FCOND_UNE: return "eq";
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case FCOND_UEQ:
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case FCOND_ONE: return "ueq";
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case FCOND_OLT:
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case FCOND_UGE: return "olt";
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case FCOND_ULT:
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case FCOND_OGE: return "ult";
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case FCOND_OLE:
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case FCOND_UGT: return "ole";
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case FCOND_ULE:
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case FCOND_OGT: return "ule";
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case FCOND_SF:
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case FCOND_ST: return "sf";
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case FCOND_NGLE:
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case FCOND_GLE: return "ngle";
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case FCOND_SEQ:
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case FCOND_SNE: return "seq";
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case FCOND_NGL:
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case FCOND_GL: return "ngl";
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case FCOND_LT:
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case FCOND_NLT: return "lt";
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case FCOND_NGE:
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case FCOND_GE: return "nge";
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case FCOND_LE:
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case FCOND_NLE: return "le";
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case FCOND_NGT:
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case FCOND_GT: return "ngt";
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}
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llvm_unreachable("Impossible condition code!");
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}
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void MipsInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
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OS << '$' << StringRef(getRegisterName(RegNo)).lower();
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}
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void MipsInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
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StringRef Annot, const MCSubtargetInfo &STI) {
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switch (MI->getOpcode()) {
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default:
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break;
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case Mips::RDHWR:
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case Mips::RDHWR64:
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O << "\t.set\tpush\n";
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O << "\t.set\tmips32r2\n";
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break;
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case Mips::Save16:
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O << "\tsave\t";
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printSaveRestore(MI, O);
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O << " # 16 bit inst\n";
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return;
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case Mips::SaveX16:
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O << "\tsave\t";
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printSaveRestore(MI, O);
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O << "\n";
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return;
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case Mips::Restore16:
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O << "\trestore\t";
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printSaveRestore(MI, O);
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O << " # 16 bit inst\n";
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return;
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case Mips::RestoreX16:
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O << "\trestore\t";
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printSaveRestore(MI, O);
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O << "\n";
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return;
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}
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// Try to print any aliases first.
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if (!printAliasInstr(MI, O) && !printAlias(*MI, O))
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printInstruction(MI, O);
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printAnnotation(O, Annot);
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switch (MI->getOpcode()) {
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default:
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break;
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case Mips::RDHWR:
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case Mips::RDHWR64:
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O << "\n\t.set\tpop";
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}
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}
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void MipsInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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const MCOperand &Op = MI->getOperand(OpNo);
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if (Op.isReg()) {
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printRegName(O, Op.getReg());
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return;
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}
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if (Op.isImm()) {
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O << formatImm(Op.getImm());
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return;
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}
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assert(Op.isExpr() && "unknown operand kind in printOperand");
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Op.getExpr()->print(O, &MAI, true);
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}
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template <unsigned Bits, unsigned Offset>
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void MipsInstPrinter::printUImm(const MCInst *MI, int opNum, raw_ostream &O) {
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const MCOperand &MO = MI->getOperand(opNum);
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if (MO.isImm()) {
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uint64_t Imm = MO.getImm();
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Imm -= Offset;
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Imm &= (1 << Bits) - 1;
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Imm += Offset;
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O << formatImm(Imm);
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return;
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}
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printOperand(MI, opNum, O);
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}
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void MipsInstPrinter::
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printMemOperand(const MCInst *MI, int opNum, raw_ostream &O) {
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// Load/Store memory operands -- imm($reg)
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// If PIC target the target is loaded as the
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// pattern lw $25,%call16($28)
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// opNum can be invalid if instruction had reglist as operand.
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// MemOperand is always last operand of instruction (base + offset).
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switch (MI->getOpcode()) {
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default:
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break;
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case Mips::SWM32_MM:
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case Mips::LWM32_MM:
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case Mips::SWM16_MM:
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case Mips::SWM16_MMR6:
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case Mips::LWM16_MM:
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case Mips::LWM16_MMR6:
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opNum = MI->getNumOperands() - 2;
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break;
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}
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printOperand(MI, opNum+1, O);
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O << "(";
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printOperand(MI, opNum, O);
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O << ")";
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}
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void MipsInstPrinter::
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printMemOperandEA(const MCInst *MI, int opNum, raw_ostream &O) {
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// when using stack locations for not load/store instructions
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// print the same way as all normal 3 operand instructions.
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printOperand(MI, opNum, O);
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O << ", ";
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printOperand(MI, opNum+1, O);
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}
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void MipsInstPrinter::
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printFCCOperand(const MCInst *MI, int opNum, raw_ostream &O) {
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const MCOperand& MO = MI->getOperand(opNum);
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O << MipsFCCToString((Mips::CondCode)MO.getImm());
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}
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void MipsInstPrinter::
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printSHFMask(const MCInst *MI, int opNum, raw_ostream &O) {
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llvm_unreachable("TODO");
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}
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bool MipsInstPrinter::printAlias(const char *Str, const MCInst &MI,
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unsigned OpNo, raw_ostream &OS) {
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OS << "\t" << Str << "\t";
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printOperand(&MI, OpNo, OS);
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return true;
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}
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bool MipsInstPrinter::printAlias(const char *Str, const MCInst &MI,
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unsigned OpNo0, unsigned OpNo1,
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raw_ostream &OS) {
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printAlias(Str, MI, OpNo0, OS);
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OS << ", ";
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printOperand(&MI, OpNo1, OS);
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return true;
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}
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bool MipsInstPrinter::printAlias(const MCInst &MI, raw_ostream &OS) {
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switch (MI.getOpcode()) {
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case Mips::BEQ:
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case Mips::BEQ_MM:
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// beq $zero, $zero, $L2 => b $L2
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// beq $r0, $zero, $L2 => beqz $r0, $L2
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return (isReg<Mips::ZERO>(MI, 0) && isReg<Mips::ZERO>(MI, 1) &&
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printAlias("b", MI, 2, OS)) ||
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(isReg<Mips::ZERO>(MI, 1) && printAlias("beqz", MI, 0, 2, OS));
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case Mips::BEQ64:
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// beq $r0, $zero, $L2 => beqz $r0, $L2
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return isReg<Mips::ZERO_64>(MI, 1) && printAlias("beqz", MI, 0, 2, OS);
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case Mips::BNE:
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case Mips::BNE_MM:
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// bne $r0, $zero, $L2 => bnez $r0, $L2
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return isReg<Mips::ZERO>(MI, 1) && printAlias("bnez", MI, 0, 2, OS);
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case Mips::BNE64:
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// bne $r0, $zero, $L2 => bnez $r0, $L2
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return isReg<Mips::ZERO_64>(MI, 1) && printAlias("bnez", MI, 0, 2, OS);
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case Mips::BGEZAL:
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// bgezal $zero, $L1 => bal $L1
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return isReg<Mips::ZERO>(MI, 0) && printAlias("bal", MI, 1, OS);
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case Mips::BC1T:
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// bc1t $fcc0, $L1 => bc1t $L1
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return isReg<Mips::FCC0>(MI, 0) && printAlias("bc1t", MI, 1, OS);
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case Mips::BC1F:
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// bc1f $fcc0, $L1 => bc1f $L1
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return isReg<Mips::FCC0>(MI, 0) && printAlias("bc1f", MI, 1, OS);
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case Mips::JALR:
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// jalr $ra, $r1 => jalr $r1
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return isReg<Mips::RA>(MI, 0) && printAlias("jalr", MI, 1, OS);
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case Mips::JALR64:
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// jalr $ra, $r1 => jalr $r1
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return isReg<Mips::RA_64>(MI, 0) && printAlias("jalr", MI, 1, OS);
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case Mips::NOR:
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case Mips::NOR_MM:
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case Mips::NOR_MMR6:
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// nor $r0, $r1, $zero => not $r0, $r1
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return isReg<Mips::ZERO>(MI, 2) && printAlias("not", MI, 0, 1, OS);
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case Mips::NOR64:
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// nor $r0, $r1, $zero => not $r0, $r1
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return isReg<Mips::ZERO_64>(MI, 2) && printAlias("not", MI, 0, 1, OS);
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case Mips::OR:
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// or $r0, $r1, $zero => move $r0, $r1
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return isReg<Mips::ZERO>(MI, 2) && printAlias("move", MI, 0, 1, OS);
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default: return false;
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}
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}
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void MipsInstPrinter::printSaveRestore(const MCInst *MI, raw_ostream &O) {
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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if (i != 0) O << ", ";
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if (MI->getOperand(i).isReg())
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printRegName(O, MI->getOperand(i).getReg());
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else
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printUImm<16>(MI, i, O);
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}
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}
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void MipsInstPrinter::
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printRegisterList(const MCInst *MI, int opNum, raw_ostream &O) {
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// - 2 because register List is always first operand of instruction and it is
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// always followed by memory operand (base + offset).
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for (int i = opNum, e = MI->getNumOperands() - 2; i != e; ++i) {
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if (i != opNum)
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O << ", ";
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printRegName(O, MI->getOperand(i).getReg());
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}
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}
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