teak-llvm/llvm/lib/CodeGen/SelectionDAG
Craig Topper 826f44b550 [TargetLowering][AMDGPU] Remove the SimplifyDemandedBits function that takes a User and OpIdx. Stop using it in AMDGPU target for simplifyI24.
As we saw in D56057 when we tried to use this function on X86, it's unsafe. It allows the operand node to have multiple users, but doesn't prevent recursing past the first node when it does have multiple users. This can cause other simplifications earlier in the graph without regard to what bits are needed by the other users of the first node. Ideally all we should do to the first node if it has multiple uses is bypass it when its not needed by the user we started from. Doing any other transformation that SimplifyDemandedBits can do like turning ZEXT/SEXT into AEXT would result in an increase in instructions.

Fortunately, we already have a function that can do just that, GetDemandedBits. It will only make transformations that involve bypassing a node.

This patch changes AMDGPU's simplifyI24, to use a combination of GetDemandedBits to handle the multiple use simplifications. And then uses the regular SimplifyDemandedBits on each operand to handle simplifications allowed when the operand only has a single use. Unfortunately, GetDemandedBits simplifies constants more aggressively than SimplifyDemandedBits. This caused the -7 constant in the changed test to be simplified to remove the upper bits. I had to modify computeKnownBits to account for this by ignoring the upper 8 bits of the input.

Differential Revision: https://reviews.llvm.org/D56087

llvm-svn: 350560
2019-01-07 19:30:43 +00:00
..
CMakeLists.txt
DAGCombiner.cpp [DAGCombiner][x86] scalarize binop followed by extractelement 2019-01-03 21:31:16 +00:00
FastISel.cpp FastIsel: take care to update iterators when removing instructions. 2018-12-17 17:25:53 +00:00
FunctionLoweringInfo.cpp AMDGPU: Fix various issues around the VirtReg2Value mapping 2018-11-30 22:55:29 +00:00
InstrEmitter.cpp [SDAG] Clarify the origin of chain in REG_SEQUENCE in comment, NFC 2018-12-17 20:30:20 +00:00
InstrEmitter.h [DebugInfo] Convert intrinsic llvm.dbg.label to MachineInstr. 2018-05-09 02:41:08 +00:00
LegalizeDAG.cpp [TargetLowering] Add ISD::ROTL/ROTR vector expansion 2018-12-13 11:20:48 +00:00
LegalizeFloatTypes.cpp [NFC] Rename minnan and maxnan to minimum and maximum 2018-10-24 22:49:55 +00:00
LegalizeIntegerTypes.cpp [LegalizeIntegerTypes] When promoting the result of an extract_vector_elt also promote the input type if necessary 2019-01-02 17:58:30 +00:00
LegalizeTypes.cpp [DAG] Don't map a TableId to itself in the ReplacedValues map 2018-06-20 16:06:09 +00:00
LegalizeTypes.h [Intrinsic] Signed Fixed Point Multiplication Intrinsic 2018-12-12 06:29:14 +00:00
LegalizeTypesGeneric.cpp [LegalizeTypes] Fix bad indentation. NFC 2018-09-23 21:17:55 +00:00
LegalizeVectorOps.cpp [LegalizeVectorOps] Add FSHL/FSHR to the list of vector operations that should be handled. 2019-01-06 07:06:35 +00:00
LegalizeVectorTypes.cpp [SelectionDAG][X86] Fix [US](ADD|SUB)SAT vector legalization, add tests 2018-12-18 13:22:53 +00:00
LLVMBuild.txt
ResourcePriorityQueue.cpp Silence a bunch of implicit fallthrough warnings 2017-12-19 22:05:25 +00:00
ScheduleDAGFast.cpp [DebugInfo] Emit undef DBG_VALUEs when SDNodes are optimised out 2018-12-10 11:20:47 +00:00
ScheduleDAGRRList.cpp ScheduleDAG: Cleanup dumping code; NFC 2018-09-19 00:23:35 +00:00
ScheduleDAGSDNodes.cpp [DebugInfo] Emit undef DBG_VALUEs when SDNodes are optimised out 2018-12-10 11:20:47 +00:00
ScheduleDAGSDNodes.h ScheduleDAG: Cleanup dumping code; NFC 2018-09-19 00:23:35 +00:00
ScheduleDAGVLIW.cpp ScheduleDAG: Cleanup dumping code; NFC 2018-09-19 00:23:35 +00:00
SDNodeDbgValue.h [DebugInfo] Emit undef DBG_VALUEs when SDNodes are optimised out 2018-12-10 11:20:47 +00:00
SelectionDAG.cpp [X86] Add INSERT_SUBVECTOR to ComputeNumSignBits 2019-01-04 20:50:59 +00:00
SelectionDAGAddressAnalysis.cpp [SelectionDAG] Teach BaseIndexOffset::match to unwrap the base after looking through an add/or 2018-11-26 20:16:33 +00:00
SelectionDAGBuilder.cpp Reversing the commit in revision 350186. Revision causes regression in 4 2019-01-01 07:28:55 +00:00
SelectionDAGBuilder.h Reversing the commit in revision 350186. Revision causes regression in 4 2019-01-01 07:28:55 +00:00
SelectionDAGDumper.cpp [Intrinsic] Signed Fixed Point Multiplication Intrinsic 2018-12-12 06:29:14 +00:00
SelectionDAGISel.cpp [SelectionDAG] Always use the version of computeKnownBits that returns a value. NFCI. 2018-12-21 14:56:18 +00:00
SelectionDAGPrinter.cpp Rename DEBUG macro to LLVM_DEBUG. 2018-05-14 12:53:11 +00:00
SelectionDAGTargetInfo.cpp
StatepointLowering.cpp [CodeGen] Prefer static frame index for STATEPOINT liveness args 2018-11-30 16:22:41 +00:00
StatepointLowering.h [IR][CodeGen] Remove dependency on EVT from IR/Function.cpp. Move EVT to CodeGen layer. 2018-03-29 17:21:10 +00:00
TargetLowering.cpp [TargetLowering][AMDGPU] Remove the SimplifyDemandedBits function that takes a User and OpIdx. Stop using it in AMDGPU target for simplifyI24. 2019-01-07 19:30:43 +00:00