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67d4c9924c
In LLVM IR, vscale can be represented with an intrinsic. For some targets, this is equivalent to the constexpr: getelementptr <vscale x 1 x i8>, <vscale x 1 x i8>* null, i32 1 This can be used to propagate the value in CodeGenPrepare. In ISel we add a node that can be legalized to one or more instructions to materialize the runtime vector length. This patch also adds SVE CodeGen support for VSCALE, which maps this node to RDVL instructions (for scaled multiples of 16bytes) or CNT[HSD] instructions (scaled multiples of 2, 4, or 8 bytes, respectively). Reviewers: rengolin, cameron.mcinally, hfinkel, sebpop, SjoerdMeijer, efriedma, lattner Reviewed by: efriedma Tags: #llvm Differential Revision: https://reviews.llvm.org/D68203 |
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| .. | ||
| CMakeLists.txt | ||
| DAGCombiner.cpp | ||
| FastISel.cpp | ||
| FunctionLoweringInfo.cpp | ||
| InstrEmitter.cpp | ||
| InstrEmitter.h | ||
| LegalizeDAG.cpp | ||
| LegalizeFloatTypes.cpp | ||
| LegalizeIntegerTypes.cpp | ||
| LegalizeTypes.cpp | ||
| LegalizeTypes.h | ||
| LegalizeTypesGeneric.cpp | ||
| LegalizeVectorOps.cpp | ||
| LegalizeVectorTypes.cpp | ||
| LLVMBuild.txt | ||
| ResourcePriorityQueue.cpp | ||
| ScheduleDAGFast.cpp | ||
| ScheduleDAGRRList.cpp | ||
| ScheduleDAGSDNodes.cpp | ||
| ScheduleDAGSDNodes.h | ||
| ScheduleDAGVLIW.cpp | ||
| SDNodeDbgValue.h | ||
| SelectionDAG.cpp | ||
| SelectionDAGAddressAnalysis.cpp | ||
| SelectionDAGBuilder.cpp | ||
| SelectionDAGBuilder.h | ||
| SelectionDAGDumper.cpp | ||
| SelectionDAGISel.cpp | ||
| SelectionDAGPrinter.cpp | ||
| SelectionDAGTargetInfo.cpp | ||
| StatepointLowering.cpp | ||
| StatepointLowering.h | ||
| TargetLowering.cpp | ||