mirror of
https://github.com/Gericom/teak-llvm.git
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5cee34013c
Future CPU will include support for prefixed instructions. These prefixed instructions are formed by a 4 byte prefix immediately followed by a 4 byte instruction effectively making an 8 byte instruction. The new instruction paddi is a prefixed form of addi. This patch adds paddi and all of the support required for that instruction. The majority of the patch deals with supporting the new prefixed instructions. The addition of paddi is mainly to allow for testing. Differential Revision: https://reviews.llvm.org/D72569
583 lines
18 KiB
C++
583 lines
18 KiB
C++
//===-- PPCInstPrinter.cpp - Convert PPC MCInst to assembly syntax --------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This class prints an PPC MCInst to a .s file.
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/PPCInstPrinter.h"
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#include "MCTargetDesc/PPCMCTargetDesc.h"
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#include "MCTargetDesc/PPCPredicates.h"
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#include "PPCInstrInfo.h"
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#include "llvm/CodeGen/TargetOpcodes.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/MC/MCSymbol.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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#define DEBUG_TYPE "asm-printer"
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// FIXME: Once the integrated assembler supports full register names, tie this
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// to the verbose-asm setting.
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static cl::opt<bool>
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FullRegNames("ppc-asm-full-reg-names", cl::Hidden, cl::init(false),
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cl::desc("Use full register names when printing assembly"));
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// Useful for testing purposes. Prints vs{31-63} as v{0-31} respectively.
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static cl::opt<bool>
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ShowVSRNumsAsVR("ppc-vsr-nums-as-vr", cl::Hidden, cl::init(false),
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cl::desc("Prints full register names with vs{31-63} as v{0-31}"));
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// Prints full register names with percent symbol.
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static cl::opt<bool>
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FullRegNamesWithPercent("ppc-reg-with-percent-prefix", cl::Hidden,
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cl::init(false),
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cl::desc("Prints full register names with percent"));
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#define PRINT_ALIAS_INSTR
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#include "PPCGenAsmWriter.inc"
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void PPCInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
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const char *RegName = getRegisterName(RegNo);
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if (RegName[0] == 'q' /* QPX */) {
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// The system toolchain on the BG/Q does not understand QPX register names
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// in .cfi_* directives, so print the name of the floating-point
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// subregister instead.
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std::string RN(RegName);
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RN[0] = 'f';
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OS << RN;
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return;
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}
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OS << RegName;
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}
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void PPCInstPrinter::printInst(const MCInst *MI, uint64_t Address,
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StringRef Annot, const MCSubtargetInfo &STI,
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raw_ostream &O) {
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// Customize printing of the addis instruction on AIX. When an operand is a
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// symbol reference, the instruction syntax is changed to look like a load
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// operation, i.e:
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// Transform: addis $rD, $rA, $src --> addis $rD, $src($rA).
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if (TT.isOSAIX() &&
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(MI->getOpcode() == PPC::ADDIS8 || MI->getOpcode() == PPC::ADDIS) &&
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MI->getOperand(2).isExpr()) {
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assert((MI->getOperand(0).isReg() && MI->getOperand(1).isReg()) &&
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"The first and the second operand of an addis instruction"
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" should be registers.");
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assert(isa<MCSymbolRefExpr>(MI->getOperand(2).getExpr()) &&
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"The third operand of an addis instruction should be a symbol "
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"reference expression if it is an expression at all.");
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O << "\taddis ";
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printOperand(MI, 0, O);
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O << ", ";
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printOperand(MI, 2, O);
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O << "(";
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printOperand(MI, 1, O);
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O << ")";
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return;
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}
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// Check for slwi/srwi mnemonics.
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if (MI->getOpcode() == PPC::RLWINM) {
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unsigned char SH = MI->getOperand(2).getImm();
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unsigned char MB = MI->getOperand(3).getImm();
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unsigned char ME = MI->getOperand(4).getImm();
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bool useSubstituteMnemonic = false;
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if (SH <= 31 && MB == 0 && ME == (31-SH)) {
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O << "\tslwi "; useSubstituteMnemonic = true;
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}
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if (SH <= 31 && MB == (32-SH) && ME == 31) {
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O << "\tsrwi "; useSubstituteMnemonic = true;
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SH = 32-SH;
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}
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if (useSubstituteMnemonic) {
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printOperand(MI, 0, O);
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O << ", ";
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printOperand(MI, 1, O);
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O << ", " << (unsigned int)SH;
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printAnnotation(O, Annot);
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return;
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}
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}
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if ((MI->getOpcode() == PPC::OR || MI->getOpcode() == PPC::OR8) &&
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MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) {
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O << "\tmr ";
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printOperand(MI, 0, O);
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O << ", ";
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printOperand(MI, 1, O);
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printAnnotation(O, Annot);
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return;
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}
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if (MI->getOpcode() == PPC::RLDICR ||
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MI->getOpcode() == PPC::RLDICR_32) {
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unsigned char SH = MI->getOperand(2).getImm();
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unsigned char ME = MI->getOperand(3).getImm();
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// rldicr RA, RS, SH, 63-SH == sldi RA, RS, SH
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if (63-SH == ME) {
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O << "\tsldi ";
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printOperand(MI, 0, O);
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O << ", ";
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printOperand(MI, 1, O);
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O << ", " << (unsigned int)SH;
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printAnnotation(O, Annot);
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return;
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}
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}
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// dcbt[st] is printed manually here because:
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// 1. The assembly syntax is different between embedded and server targets
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// 2. We must print the short mnemonics for TH == 0 because the
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// embedded/server syntax default will not be stable across assemblers
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// The syntax for dcbt is:
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// dcbt ra, rb, th [server]
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// dcbt th, ra, rb [embedded]
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// where th can be omitted when it is 0. dcbtst is the same.
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if (MI->getOpcode() == PPC::DCBT || MI->getOpcode() == PPC::DCBTST) {
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unsigned char TH = MI->getOperand(0).getImm();
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O << "\tdcbt";
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if (MI->getOpcode() == PPC::DCBTST)
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O << "st";
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if (TH == 16)
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O << "t";
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O << " ";
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bool IsBookE = STI.getFeatureBits()[PPC::FeatureBookE];
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if (IsBookE && TH != 0 && TH != 16)
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O << (unsigned int) TH << ", ";
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printOperand(MI, 1, O);
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O << ", ";
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printOperand(MI, 2, O);
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if (!IsBookE && TH != 0 && TH != 16)
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O << ", " << (unsigned int) TH;
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printAnnotation(O, Annot);
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return;
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}
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if (MI->getOpcode() == PPC::DCBF) {
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unsigned char L = MI->getOperand(0).getImm();
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if (!L || L == 1 || L == 3) {
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O << "\tdcbf";
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if (L == 1 || L == 3)
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O << "l";
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if (L == 3)
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O << "p";
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O << " ";
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printOperand(MI, 1, O);
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O << ", ";
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printOperand(MI, 2, O);
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printAnnotation(O, Annot);
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return;
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}
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}
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if (!printAliasInstr(MI, O))
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printInstruction(MI, Address, O);
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printAnnotation(O, Annot);
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}
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void PPCInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O,
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const char *Modifier) {
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unsigned Code = MI->getOperand(OpNo).getImm();
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if (StringRef(Modifier) == "cc") {
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switch ((PPC::Predicate)Code) {
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case PPC::PRED_LT_MINUS:
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case PPC::PRED_LT_PLUS:
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case PPC::PRED_LT:
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O << "lt";
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return;
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case PPC::PRED_LE_MINUS:
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case PPC::PRED_LE_PLUS:
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case PPC::PRED_LE:
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O << "le";
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return;
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case PPC::PRED_EQ_MINUS:
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case PPC::PRED_EQ_PLUS:
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case PPC::PRED_EQ:
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O << "eq";
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return;
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case PPC::PRED_GE_MINUS:
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case PPC::PRED_GE_PLUS:
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case PPC::PRED_GE:
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O << "ge";
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return;
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case PPC::PRED_GT_MINUS:
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case PPC::PRED_GT_PLUS:
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case PPC::PRED_GT:
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O << "gt";
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return;
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case PPC::PRED_NE_MINUS:
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case PPC::PRED_NE_PLUS:
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case PPC::PRED_NE:
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O << "ne";
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return;
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case PPC::PRED_UN_MINUS:
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case PPC::PRED_UN_PLUS:
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case PPC::PRED_UN:
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O << "un";
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return;
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case PPC::PRED_NU_MINUS:
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case PPC::PRED_NU_PLUS:
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case PPC::PRED_NU:
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O << "nu";
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return;
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case PPC::PRED_BIT_SET:
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case PPC::PRED_BIT_UNSET:
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llvm_unreachable("Invalid use of bit predicate code");
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}
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llvm_unreachable("Invalid predicate code");
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}
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if (StringRef(Modifier) == "pm") {
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switch ((PPC::Predicate)Code) {
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case PPC::PRED_LT:
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case PPC::PRED_LE:
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case PPC::PRED_EQ:
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case PPC::PRED_GE:
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case PPC::PRED_GT:
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case PPC::PRED_NE:
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case PPC::PRED_UN:
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case PPC::PRED_NU:
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return;
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case PPC::PRED_LT_MINUS:
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case PPC::PRED_LE_MINUS:
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case PPC::PRED_EQ_MINUS:
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case PPC::PRED_GE_MINUS:
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case PPC::PRED_GT_MINUS:
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case PPC::PRED_NE_MINUS:
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case PPC::PRED_UN_MINUS:
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case PPC::PRED_NU_MINUS:
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O << "-";
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return;
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case PPC::PRED_LT_PLUS:
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case PPC::PRED_LE_PLUS:
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case PPC::PRED_EQ_PLUS:
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case PPC::PRED_GE_PLUS:
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case PPC::PRED_GT_PLUS:
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case PPC::PRED_NE_PLUS:
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case PPC::PRED_UN_PLUS:
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case PPC::PRED_NU_PLUS:
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O << "+";
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return;
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case PPC::PRED_BIT_SET:
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case PPC::PRED_BIT_UNSET:
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llvm_unreachable("Invalid use of bit predicate code");
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}
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llvm_unreachable("Invalid predicate code");
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}
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assert(StringRef(Modifier) == "reg" &&
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"Need to specify 'cc', 'pm' or 'reg' as predicate op modifier!");
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printOperand(MI, OpNo+1, O);
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}
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void PPCInstPrinter::printATBitsAsHint(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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unsigned Code = MI->getOperand(OpNo).getImm();
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if (Code == 2)
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O << "-";
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else if (Code == 3)
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O << "+";
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}
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void PPCInstPrinter::printU1ImmOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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unsigned int Value = MI->getOperand(OpNo).getImm();
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assert(Value <= 1 && "Invalid u1imm argument!");
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O << (unsigned int)Value;
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}
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void PPCInstPrinter::printU2ImmOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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unsigned int Value = MI->getOperand(OpNo).getImm();
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assert(Value <= 3 && "Invalid u2imm argument!");
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O << (unsigned int)Value;
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}
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void PPCInstPrinter::printU3ImmOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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unsigned int Value = MI->getOperand(OpNo).getImm();
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assert(Value <= 8 && "Invalid u3imm argument!");
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O << (unsigned int)Value;
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}
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void PPCInstPrinter::printU4ImmOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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unsigned int Value = MI->getOperand(OpNo).getImm();
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assert(Value <= 15 && "Invalid u4imm argument!");
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O << (unsigned int)Value;
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}
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void PPCInstPrinter::printS5ImmOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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int Value = MI->getOperand(OpNo).getImm();
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Value = SignExtend32<5>(Value);
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O << (int)Value;
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}
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void PPCInstPrinter::printImmZeroOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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unsigned int Value = MI->getOperand(OpNo).getImm();
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assert(Value == 0 && "Operand must be zero");
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O << (unsigned int)Value;
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}
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void PPCInstPrinter::printU5ImmOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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unsigned int Value = MI->getOperand(OpNo).getImm();
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assert(Value <= 31 && "Invalid u5imm argument!");
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O << (unsigned int)Value;
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}
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void PPCInstPrinter::printU6ImmOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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unsigned int Value = MI->getOperand(OpNo).getImm();
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assert(Value <= 63 && "Invalid u6imm argument!");
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O << (unsigned int)Value;
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}
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void PPCInstPrinter::printU7ImmOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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unsigned int Value = MI->getOperand(OpNo).getImm();
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assert(Value <= 127 && "Invalid u7imm argument!");
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O << (unsigned int)Value;
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}
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// Operands of BUILD_VECTOR are signed and we use this to print operands
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// of XXSPLTIB which are unsigned. So we simply truncate to 8 bits and
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// print as unsigned.
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void PPCInstPrinter::printU8ImmOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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unsigned char Value = MI->getOperand(OpNo).getImm();
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O << (unsigned int)Value;
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}
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void PPCInstPrinter::printU10ImmOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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unsigned short Value = MI->getOperand(OpNo).getImm();
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assert(Value <= 1023 && "Invalid u10imm argument!");
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O << (unsigned short)Value;
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}
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void PPCInstPrinter::printU12ImmOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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unsigned short Value = MI->getOperand(OpNo).getImm();
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assert(Value <= 4095 && "Invalid u12imm argument!");
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O << (unsigned short)Value;
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}
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void PPCInstPrinter::printS16ImmOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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if (MI->getOperand(OpNo).isImm())
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O << (short)MI->getOperand(OpNo).getImm();
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else
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printOperand(MI, OpNo, O);
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}
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void PPCInstPrinter::printS34ImmOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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long long Value = MI->getOperand(OpNo).getImm();
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assert(isInt<34>(Value) && "Invalid s34imm argument!");
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O << (long long)Value;
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}
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void PPCInstPrinter::printU16ImmOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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if (MI->getOperand(OpNo).isImm())
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O << (unsigned short)MI->getOperand(OpNo).getImm();
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else
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printOperand(MI, OpNo, O);
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}
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void PPCInstPrinter::printBranchOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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if (!MI->getOperand(OpNo).isImm())
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return printOperand(MI, OpNo, O);
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// Branches can take an immediate operand. This is used by the branch
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// selection pass to print .+8, an eight byte displacement from the PC.
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O << ".";
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int32_t Imm = SignExtend32<32>((unsigned)MI->getOperand(OpNo).getImm() << 2);
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if (Imm >= 0)
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O << "+";
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O << Imm;
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}
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void PPCInstPrinter::printAbsBranchOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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if (!MI->getOperand(OpNo).isImm())
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return printOperand(MI, OpNo, O);
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O << SignExtend32<32>((unsigned)MI->getOperand(OpNo).getImm() << 2);
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}
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void PPCInstPrinter::printcrbitm(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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unsigned CCReg = MI->getOperand(OpNo).getReg();
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unsigned RegNo;
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switch (CCReg) {
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default: llvm_unreachable("Unknown CR register");
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case PPC::CR0: RegNo = 0; break;
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case PPC::CR1: RegNo = 1; break;
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case PPC::CR2: RegNo = 2; break;
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case PPC::CR3: RegNo = 3; break;
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case PPC::CR4: RegNo = 4; break;
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case PPC::CR5: RegNo = 5; break;
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case PPC::CR6: RegNo = 6; break;
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case PPC::CR7: RegNo = 7; break;
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}
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O << (0x80 >> RegNo);
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}
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void PPCInstPrinter::printMemRegImm(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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printS16ImmOperand(MI, OpNo, O);
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O << '(';
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if (MI->getOperand(OpNo+1).getReg() == PPC::R0)
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O << "0";
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else
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printOperand(MI, OpNo+1, O);
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O << ')';
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}
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void PPCInstPrinter::printMemRegReg(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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// When used as the base register, r0 reads constant zero rather than
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// the value contained in the register. For this reason, the darwin
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// assembler requires that we print r0 as 0 (no r) when used as the base.
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if (MI->getOperand(OpNo).getReg() == PPC::R0)
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O << "0";
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else
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printOperand(MI, OpNo, O);
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O << ", ";
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printOperand(MI, OpNo+1, O);
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}
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void PPCInstPrinter::printTLSCall(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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// On PPC64, VariantKind is VK_None, but on PPC32, it's VK_PLT, and it must
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// come at the _end_ of the expression.
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const MCOperand &Op = MI->getOperand(OpNo);
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const MCSymbolRefExpr *RefExp = nullptr;
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const MCConstantExpr *ConstExp = nullptr;
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if (const MCBinaryExpr *BinExpr = dyn_cast<MCBinaryExpr>(Op.getExpr())) {
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RefExp = cast<MCSymbolRefExpr>(BinExpr->getLHS());
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ConstExp = cast<MCConstantExpr>(BinExpr->getRHS());
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} else
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RefExp = cast<MCSymbolRefExpr>(Op.getExpr());
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O << RefExp->getSymbol().getName();
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O << '(';
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printOperand(MI, OpNo+1, O);
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O << ')';
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if (RefExp->getKind() != MCSymbolRefExpr::VK_None)
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O << '@' << MCSymbolRefExpr::getVariantKindName(RefExp->getKind());
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if (ConstExp != nullptr)
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O << '+' << ConstExp->getValue();
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}
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/// showRegistersWithPercentPrefix - Check if this register name should be
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/// printed with a percentage symbol as prefix.
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bool PPCInstPrinter::showRegistersWithPercentPrefix(const char *RegName) const {
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if (!FullRegNamesWithPercent || TT.isOSDarwin() || TT.getOS() == Triple::AIX)
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return false;
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switch (RegName[0]) {
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default:
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return false;
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case 'r':
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case 'f':
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case 'q':
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case 'v':
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case 'c':
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return true;
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}
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}
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/// getVerboseConditionalRegName - This method expands the condition register
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/// when requested explicitly or targetting Darwin.
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const char *PPCInstPrinter::getVerboseConditionRegName(unsigned RegNum,
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unsigned RegEncoding)
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const {
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if (!TT.isOSDarwin() && !FullRegNames)
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return nullptr;
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if (RegNum < PPC::CR0EQ || RegNum > PPC::CR7UN)
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return nullptr;
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const char *CRBits[] = {
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"lt", "gt", "eq", "un",
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"4*cr1+lt", "4*cr1+gt", "4*cr1+eq", "4*cr1+un",
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"4*cr2+lt", "4*cr2+gt", "4*cr2+eq", "4*cr2+un",
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"4*cr3+lt", "4*cr3+gt", "4*cr3+eq", "4*cr3+un",
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"4*cr4+lt", "4*cr4+gt", "4*cr4+eq", "4*cr4+un",
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"4*cr5+lt", "4*cr5+gt", "4*cr5+eq", "4*cr5+un",
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"4*cr6+lt", "4*cr6+gt", "4*cr6+eq", "4*cr6+un",
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"4*cr7+lt", "4*cr7+gt", "4*cr7+eq", "4*cr7+un"
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};
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return CRBits[RegEncoding];
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}
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|
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// showRegistersWithPrefix - This method determines whether registers
|
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// should be number-only or include the prefix.
|
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bool PPCInstPrinter::showRegistersWithPrefix() const {
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if (TT.getOS() == Triple::AIX)
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return false;
|
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return TT.isOSDarwin() || FullRegNamesWithPercent || FullRegNames;
|
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}
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|
|
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void PPCInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
|
|
raw_ostream &O) {
|
|
const MCOperand &Op = MI->getOperand(OpNo);
|
|
if (Op.isReg()) {
|
|
unsigned Reg = Op.getReg();
|
|
if (!ShowVSRNumsAsVR)
|
|
Reg = PPCInstrInfo::getRegNumForOperand(MII.get(MI->getOpcode()),
|
|
Reg, OpNo);
|
|
|
|
const char *RegName;
|
|
RegName = getVerboseConditionRegName(Reg, MRI.getEncodingValue(Reg));
|
|
if (RegName == nullptr)
|
|
RegName = getRegisterName(Reg);
|
|
if (showRegistersWithPercentPrefix(RegName))
|
|
O << "%";
|
|
if (!showRegistersWithPrefix())
|
|
RegName = PPCRegisterInfo::stripRegisterPrefix(RegName);
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|
|
|
O << RegName;
|
|
return;
|
|
}
|
|
|
|
if (Op.isImm()) {
|
|
O << Op.getImm();
|
|
return;
|
|
}
|
|
|
|
assert(Op.isExpr() && "unknown operand kind in printOperand");
|
|
Op.getExpr()->print(O, &MAI);
|
|
}
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