mirror of
https://github.com/Gericom/teak-llvm.git
synced 2025-06-25 22:38:56 -04:00
a7b00058e0
Summary: Moving SMRD to VMEM in SIFixSGPRCopies is rather bad for performance if the load is really uniform. So select the scalar load intrinsics directly to either VMEM or SMRD buffer loads based on divergence analysis. If an offset happens to end up in a VGPR -- either because a floating point calculation was involved, or due to other remaining deficiencies in SIFixSGPRCopies -- we use v_readfirstlane. There is some unrelated churn in tests since we now select MUBUF offsets in a unified way with non-scalar buffer loads. Change-Id: I170e6816323beb1348677b358c9d380865cd1a19 Reviewers: arsenm, alex-t, rampitec, tpr Subscribers: kzhuravl, jvesely, wdng, yaxunl, dstuttard, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D53283 llvm-svn: 348050
971 lines
30 KiB
C++
971 lines
30 KiB
C++
//===- AMDGPUBaseInfo.cpp - AMDGPU Base encoding information --------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPUBaseInfo.h"
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#include "AMDGPUTargetTransformInfo.h"
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#include "AMDGPU.h"
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#include "SIDefines.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/ADT/Triple.h"
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#include "llvm/BinaryFormat/ELF.h"
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#include "llvm/CodeGen/MachineMemOperand.h"
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#include "llvm/IR/Attributes.h"
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#include "llvm/IR/Constants.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/GlobalValue.h"
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#include "llvm/IR/Instruction.h"
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#include "llvm/IR/LLVMContext.h"
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#include "llvm/IR/Module.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCInstrDesc.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCSectionELF.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/MC/SubtargetFeature.h"
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#include "llvm/Support/Casting.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/MathExtras.h"
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#include <algorithm>
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#include <cassert>
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#include <cstdint>
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#include <cstring>
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#include <utility>
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#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
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#define GET_INSTRINFO_NAMED_OPS
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#define GET_INSTRMAP_INFO
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#include "AMDGPUGenInstrInfo.inc"
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#undef GET_INSTRMAP_INFO
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#undef GET_INSTRINFO_NAMED_OPS
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namespace {
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/// \returns Bit mask for given bit \p Shift and bit \p Width.
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unsigned getBitMask(unsigned Shift, unsigned Width) {
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return ((1 << Width) - 1) << Shift;
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}
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/// Packs \p Src into \p Dst for given bit \p Shift and bit \p Width.
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///
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/// \returns Packed \p Dst.
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unsigned packBits(unsigned Src, unsigned Dst, unsigned Shift, unsigned Width) {
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Dst &= ~(1 << Shift) & ~getBitMask(Shift, Width);
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Dst |= (Src << Shift) & getBitMask(Shift, Width);
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return Dst;
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}
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/// Unpacks bits from \p Src for given bit \p Shift and bit \p Width.
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///
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/// \returns Unpacked bits.
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unsigned unpackBits(unsigned Src, unsigned Shift, unsigned Width) {
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return (Src & getBitMask(Shift, Width)) >> Shift;
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}
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/// \returns Vmcnt bit shift (lower bits).
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unsigned getVmcntBitShiftLo() { return 0; }
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/// \returns Vmcnt bit width (lower bits).
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unsigned getVmcntBitWidthLo() { return 4; }
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/// \returns Expcnt bit shift.
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unsigned getExpcntBitShift() { return 4; }
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/// \returns Expcnt bit width.
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unsigned getExpcntBitWidth() { return 3; }
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/// \returns Lgkmcnt bit shift.
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unsigned getLgkmcntBitShift() { return 8; }
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/// \returns Lgkmcnt bit width.
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unsigned getLgkmcntBitWidth() { return 4; }
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/// \returns Vmcnt bit shift (higher bits).
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unsigned getVmcntBitShiftHi() { return 14; }
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/// \returns Vmcnt bit width (higher bits).
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unsigned getVmcntBitWidthHi() { return 2; }
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} // end namespace anonymous
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namespace llvm {
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namespace AMDGPU {
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struct MIMGInfo {
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uint16_t Opcode;
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uint16_t BaseOpcode;
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uint8_t MIMGEncoding;
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uint8_t VDataDwords;
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uint8_t VAddrDwords;
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};
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#define GET_MIMGBaseOpcodesTable_IMPL
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#define GET_MIMGDimInfoTable_IMPL
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#define GET_MIMGInfoTable_IMPL
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#define GET_MIMGLZMappingTable_IMPL
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#include "AMDGPUGenSearchableTables.inc"
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int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding,
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unsigned VDataDwords, unsigned VAddrDwords) {
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const MIMGInfo *Info = getMIMGOpcodeHelper(BaseOpcode, MIMGEncoding,
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VDataDwords, VAddrDwords);
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return Info ? Info->Opcode : -1;
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}
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int getMaskedMIMGOp(unsigned Opc, unsigned NewChannels) {
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const MIMGInfo *OrigInfo = getMIMGInfo(Opc);
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const MIMGInfo *NewInfo =
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getMIMGOpcodeHelper(OrigInfo->BaseOpcode, OrigInfo->MIMGEncoding,
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NewChannels, OrigInfo->VAddrDwords);
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return NewInfo ? NewInfo->Opcode : -1;
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}
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// Wrapper for Tablegen'd function. enum Subtarget is not defined in any
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// header files, so we need to wrap it in a function that takes unsigned
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// instead.
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int getMCOpcode(uint16_t Opcode, unsigned Gen) {
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return getMCOpcodeGen(Opcode, static_cast<Subtarget>(Gen));
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}
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namespace IsaInfo {
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void streamIsaVersion(const MCSubtargetInfo *STI, raw_ostream &Stream) {
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auto TargetTriple = STI->getTargetTriple();
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auto Version = getIsaVersion(STI->getCPU());
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Stream << TargetTriple.getArchName() << '-'
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<< TargetTriple.getVendorName() << '-'
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<< TargetTriple.getOSName() << '-'
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<< TargetTriple.getEnvironmentName() << '-'
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<< "gfx"
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<< Version.Major
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<< Version.Minor
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<< Version.Stepping;
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if (hasXNACK(*STI))
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Stream << "+xnack";
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if (hasSRAMECC(*STI))
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Stream << "+sram-ecc";
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Stream.flush();
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}
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bool hasCodeObjectV3(const MCSubtargetInfo *STI) {
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return STI->getTargetTriple().getOS() == Triple::AMDHSA &&
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STI->getFeatureBits().test(FeatureCodeObjectV3);
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}
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unsigned getWavefrontSize(const MCSubtargetInfo *STI) {
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if (STI->getFeatureBits().test(FeatureWavefrontSize16))
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return 16;
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if (STI->getFeatureBits().test(FeatureWavefrontSize32))
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return 32;
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return 64;
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}
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unsigned getLocalMemorySize(const MCSubtargetInfo *STI) {
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if (STI->getFeatureBits().test(FeatureLocalMemorySize32768))
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return 32768;
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if (STI->getFeatureBits().test(FeatureLocalMemorySize65536))
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return 65536;
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return 0;
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}
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unsigned getEUsPerCU(const MCSubtargetInfo *STI) {
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return 4;
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}
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unsigned getMaxWorkGroupsPerCU(const MCSubtargetInfo *STI,
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unsigned FlatWorkGroupSize) {
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if (!STI->getFeatureBits().test(FeatureGCN))
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return 8;
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unsigned N = getWavesPerWorkGroup(STI, FlatWorkGroupSize);
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if (N == 1)
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return 40;
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N = 40 / N;
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return std::min(N, 16u);
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}
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unsigned getMaxWavesPerCU(const MCSubtargetInfo *STI) {
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return getMaxWavesPerEU() * getEUsPerCU(STI);
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}
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unsigned getMaxWavesPerCU(const MCSubtargetInfo *STI,
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unsigned FlatWorkGroupSize) {
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return getWavesPerWorkGroup(STI, FlatWorkGroupSize);
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}
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unsigned getMinWavesPerEU(const MCSubtargetInfo *STI) {
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return 1;
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}
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unsigned getMaxWavesPerEU() {
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// FIXME: Need to take scratch memory into account.
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return 10;
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}
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unsigned getMaxWavesPerEU(const MCSubtargetInfo *STI,
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unsigned FlatWorkGroupSize) {
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return alignTo(getMaxWavesPerCU(STI, FlatWorkGroupSize),
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getEUsPerCU(STI)) / getEUsPerCU(STI);
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}
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unsigned getMinFlatWorkGroupSize(const MCSubtargetInfo *STI) {
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return 1;
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}
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unsigned getMaxFlatWorkGroupSize(const MCSubtargetInfo *STI) {
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return 2048;
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}
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unsigned getWavesPerWorkGroup(const MCSubtargetInfo *STI,
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unsigned FlatWorkGroupSize) {
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return alignTo(FlatWorkGroupSize, getWavefrontSize(STI)) /
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getWavefrontSize(STI);
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}
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unsigned getSGPRAllocGranule(const MCSubtargetInfo *STI) {
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IsaVersion Version = getIsaVersion(STI->getCPU());
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if (Version.Major >= 8)
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return 16;
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return 8;
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}
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unsigned getSGPREncodingGranule(const MCSubtargetInfo *STI) {
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return 8;
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}
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unsigned getTotalNumSGPRs(const MCSubtargetInfo *STI) {
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IsaVersion Version = getIsaVersion(STI->getCPU());
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if (Version.Major >= 8)
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return 800;
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return 512;
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}
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unsigned getAddressableNumSGPRs(const MCSubtargetInfo *STI) {
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if (STI->getFeatureBits().test(FeatureSGPRInitBug))
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return FIXED_NUM_SGPRS_FOR_INIT_BUG;
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IsaVersion Version = getIsaVersion(STI->getCPU());
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if (Version.Major >= 8)
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return 102;
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return 104;
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}
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unsigned getMinNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU) {
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assert(WavesPerEU != 0);
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if (WavesPerEU >= getMaxWavesPerEU())
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return 0;
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unsigned MinNumSGPRs = getTotalNumSGPRs(STI) / (WavesPerEU + 1);
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if (STI->getFeatureBits().test(FeatureTrapHandler))
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MinNumSGPRs -= std::min(MinNumSGPRs, (unsigned)TRAP_NUM_SGPRS);
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MinNumSGPRs = alignDown(MinNumSGPRs, getSGPRAllocGranule(STI)) + 1;
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return std::min(MinNumSGPRs, getAddressableNumSGPRs(STI));
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}
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unsigned getMaxNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU,
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bool Addressable) {
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assert(WavesPerEU != 0);
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IsaVersion Version = getIsaVersion(STI->getCPU());
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unsigned AddressableNumSGPRs = getAddressableNumSGPRs(STI);
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if (Version.Major >= 8 && !Addressable)
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AddressableNumSGPRs = 112;
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unsigned MaxNumSGPRs = getTotalNumSGPRs(STI) / WavesPerEU;
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if (STI->getFeatureBits().test(FeatureTrapHandler))
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MaxNumSGPRs -= std::min(MaxNumSGPRs, (unsigned)TRAP_NUM_SGPRS);
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MaxNumSGPRs = alignDown(MaxNumSGPRs, getSGPRAllocGranule(STI));
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return std::min(MaxNumSGPRs, AddressableNumSGPRs);
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}
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unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,
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bool FlatScrUsed, bool XNACKUsed) {
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unsigned ExtraSGPRs = 0;
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if (VCCUsed)
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ExtraSGPRs = 2;
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IsaVersion Version = getIsaVersion(STI->getCPU());
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if (Version.Major < 8) {
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if (FlatScrUsed)
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ExtraSGPRs = 4;
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} else {
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if (XNACKUsed)
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ExtraSGPRs = 4;
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if (FlatScrUsed)
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ExtraSGPRs = 6;
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}
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return ExtraSGPRs;
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}
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unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,
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bool FlatScrUsed) {
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return getNumExtraSGPRs(STI, VCCUsed, FlatScrUsed,
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STI->getFeatureBits().test(AMDGPU::FeatureXNACK));
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}
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unsigned getNumSGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs) {
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NumSGPRs = alignTo(std::max(1u, NumSGPRs), getSGPREncodingGranule(STI));
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// SGPRBlocks is actual number of SGPR blocks minus 1.
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return NumSGPRs / getSGPREncodingGranule(STI) - 1;
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}
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unsigned getVGPRAllocGranule(const MCSubtargetInfo *STI) {
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return 4;
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}
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unsigned getVGPREncodingGranule(const MCSubtargetInfo *STI) {
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return getVGPRAllocGranule(STI);
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}
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unsigned getTotalNumVGPRs(const MCSubtargetInfo *STI) {
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return 256;
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}
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unsigned getAddressableNumVGPRs(const MCSubtargetInfo *STI) {
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return getTotalNumVGPRs(STI);
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}
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unsigned getMinNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU) {
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assert(WavesPerEU != 0);
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if (WavesPerEU >= getMaxWavesPerEU())
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return 0;
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unsigned MinNumVGPRs =
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alignDown(getTotalNumVGPRs(STI) / (WavesPerEU + 1),
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getVGPRAllocGranule(STI)) + 1;
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return std::min(MinNumVGPRs, getAddressableNumVGPRs(STI));
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}
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unsigned getMaxNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU) {
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assert(WavesPerEU != 0);
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unsigned MaxNumVGPRs = alignDown(getTotalNumVGPRs(STI) / WavesPerEU,
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getVGPRAllocGranule(STI));
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unsigned AddressableNumVGPRs = getAddressableNumVGPRs(STI);
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return std::min(MaxNumVGPRs, AddressableNumVGPRs);
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}
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unsigned getNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumVGPRs) {
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NumVGPRs = alignTo(std::max(1u, NumVGPRs), getVGPREncodingGranule(STI));
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// VGPRBlocks is actual number of VGPR blocks minus 1.
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return NumVGPRs / getVGPREncodingGranule(STI) - 1;
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}
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} // end namespace IsaInfo
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void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header,
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const MCSubtargetInfo *STI) {
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IsaVersion Version = getIsaVersion(STI->getCPU());
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memset(&Header, 0, sizeof(Header));
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Header.amd_kernel_code_version_major = 1;
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Header.amd_kernel_code_version_minor = 2;
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Header.amd_machine_kind = 1; // AMD_MACHINE_KIND_AMDGPU
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Header.amd_machine_version_major = Version.Major;
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Header.amd_machine_version_minor = Version.Minor;
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Header.amd_machine_version_stepping = Version.Stepping;
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Header.kernel_code_entry_byte_offset = sizeof(Header);
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// wavefront_size is specified as a power of 2: 2^6 = 64 threads.
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Header.wavefront_size = 6;
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// If the code object does not support indirect functions, then the value must
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// be 0xffffffff.
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Header.call_convention = -1;
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// These alignment values are specified in powers of two, so alignment =
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// 2^n. The minimum alignment is 2^4 = 16.
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Header.kernarg_segment_alignment = 4;
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Header.group_segment_alignment = 4;
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Header.private_segment_alignment = 4;
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}
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amdhsa::kernel_descriptor_t getDefaultAmdhsaKernelDescriptor() {
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amdhsa::kernel_descriptor_t KD;
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memset(&KD, 0, sizeof(KD));
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AMDHSA_BITS_SET(KD.compute_pgm_rsrc1,
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amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64,
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amdhsa::FLOAT_DENORM_MODE_FLUSH_NONE);
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AMDHSA_BITS_SET(KD.compute_pgm_rsrc1,
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amdhsa::COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP, 1);
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AMDHSA_BITS_SET(KD.compute_pgm_rsrc1,
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amdhsa::COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE, 1);
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AMDHSA_BITS_SET(KD.compute_pgm_rsrc2,
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amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X, 1);
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return KD;
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}
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bool isGroupSegment(const GlobalValue *GV) {
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return GV->getType()->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS;
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}
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bool isGlobalSegment(const GlobalValue *GV) {
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return GV->getType()->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS;
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}
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bool isReadOnlySegment(const GlobalValue *GV) {
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return GV->getType()->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS ||
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GV->getType()->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS_32BIT;
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}
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bool shouldEmitConstantsToTextSection(const Triple &TT) {
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return TT.getOS() != Triple::AMDHSA;
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}
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int getIntegerAttribute(const Function &F, StringRef Name, int Default) {
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Attribute A = F.getFnAttribute(Name);
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int Result = Default;
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if (A.isStringAttribute()) {
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StringRef Str = A.getValueAsString();
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if (Str.getAsInteger(0, Result)) {
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LLVMContext &Ctx = F.getContext();
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Ctx.emitError("can't parse integer attribute " + Name);
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}
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}
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return Result;
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}
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std::pair<int, int> getIntegerPairAttribute(const Function &F,
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StringRef Name,
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std::pair<int, int> Default,
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bool OnlyFirstRequired) {
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Attribute A = F.getFnAttribute(Name);
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if (!A.isStringAttribute())
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return Default;
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LLVMContext &Ctx = F.getContext();
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std::pair<int, int> Ints = Default;
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std::pair<StringRef, StringRef> Strs = A.getValueAsString().split(',');
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if (Strs.first.trim().getAsInteger(0, Ints.first)) {
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Ctx.emitError("can't parse first integer attribute " + Name);
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return Default;
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}
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if (Strs.second.trim().getAsInteger(0, Ints.second)) {
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if (!OnlyFirstRequired || !Strs.second.trim().empty()) {
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Ctx.emitError("can't parse second integer attribute " + Name);
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return Default;
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}
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}
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return Ints;
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|
}
|
|
|
|
unsigned getVmcntBitMask(const IsaVersion &Version) {
|
|
unsigned VmcntLo = (1 << getVmcntBitWidthLo()) - 1;
|
|
if (Version.Major < 9)
|
|
return VmcntLo;
|
|
|
|
unsigned VmcntHi = ((1 << getVmcntBitWidthHi()) - 1) << getVmcntBitWidthLo();
|
|
return VmcntLo | VmcntHi;
|
|
}
|
|
|
|
unsigned getExpcntBitMask(const IsaVersion &Version) {
|
|
return (1 << getExpcntBitWidth()) - 1;
|
|
}
|
|
|
|
unsigned getLgkmcntBitMask(const IsaVersion &Version) {
|
|
return (1 << getLgkmcntBitWidth()) - 1;
|
|
}
|
|
|
|
unsigned getWaitcntBitMask(const IsaVersion &Version) {
|
|
unsigned VmcntLo = getBitMask(getVmcntBitShiftLo(), getVmcntBitWidthLo());
|
|
unsigned Expcnt = getBitMask(getExpcntBitShift(), getExpcntBitWidth());
|
|
unsigned Lgkmcnt = getBitMask(getLgkmcntBitShift(), getLgkmcntBitWidth());
|
|
unsigned Waitcnt = VmcntLo | Expcnt | Lgkmcnt;
|
|
if (Version.Major < 9)
|
|
return Waitcnt;
|
|
|
|
unsigned VmcntHi = getBitMask(getVmcntBitShiftHi(), getVmcntBitWidthHi());
|
|
return Waitcnt | VmcntHi;
|
|
}
|
|
|
|
unsigned decodeVmcnt(const IsaVersion &Version, unsigned Waitcnt) {
|
|
unsigned VmcntLo =
|
|
unpackBits(Waitcnt, getVmcntBitShiftLo(), getVmcntBitWidthLo());
|
|
if (Version.Major < 9)
|
|
return VmcntLo;
|
|
|
|
unsigned VmcntHi =
|
|
unpackBits(Waitcnt, getVmcntBitShiftHi(), getVmcntBitWidthHi());
|
|
VmcntHi <<= getVmcntBitWidthLo();
|
|
return VmcntLo | VmcntHi;
|
|
}
|
|
|
|
unsigned decodeExpcnt(const IsaVersion &Version, unsigned Waitcnt) {
|
|
return unpackBits(Waitcnt, getExpcntBitShift(), getExpcntBitWidth());
|
|
}
|
|
|
|
unsigned decodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt) {
|
|
return unpackBits(Waitcnt, getLgkmcntBitShift(), getLgkmcntBitWidth());
|
|
}
|
|
|
|
void decodeWaitcnt(const IsaVersion &Version, unsigned Waitcnt,
|
|
unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt) {
|
|
Vmcnt = decodeVmcnt(Version, Waitcnt);
|
|
Expcnt = decodeExpcnt(Version, Waitcnt);
|
|
Lgkmcnt = decodeLgkmcnt(Version, Waitcnt);
|
|
}
|
|
|
|
Waitcnt decodeWaitcnt(const IsaVersion &Version, unsigned Encoded) {
|
|
Waitcnt Decoded;
|
|
Decoded.VmCnt = decodeVmcnt(Version, Encoded);
|
|
Decoded.ExpCnt = decodeExpcnt(Version, Encoded);
|
|
Decoded.LgkmCnt = decodeLgkmcnt(Version, Encoded);
|
|
return Decoded;
|
|
}
|
|
|
|
unsigned encodeVmcnt(const IsaVersion &Version, unsigned Waitcnt,
|
|
unsigned Vmcnt) {
|
|
Waitcnt =
|
|
packBits(Vmcnt, Waitcnt, getVmcntBitShiftLo(), getVmcntBitWidthLo());
|
|
if (Version.Major < 9)
|
|
return Waitcnt;
|
|
|
|
Vmcnt >>= getVmcntBitWidthLo();
|
|
return packBits(Vmcnt, Waitcnt, getVmcntBitShiftHi(), getVmcntBitWidthHi());
|
|
}
|
|
|
|
unsigned encodeExpcnt(const IsaVersion &Version, unsigned Waitcnt,
|
|
unsigned Expcnt) {
|
|
return packBits(Expcnt, Waitcnt, getExpcntBitShift(), getExpcntBitWidth());
|
|
}
|
|
|
|
unsigned encodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt,
|
|
unsigned Lgkmcnt) {
|
|
return packBits(Lgkmcnt, Waitcnt, getLgkmcntBitShift(), getLgkmcntBitWidth());
|
|
}
|
|
|
|
unsigned encodeWaitcnt(const IsaVersion &Version,
|
|
unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt) {
|
|
unsigned Waitcnt = getWaitcntBitMask(Version);
|
|
Waitcnt = encodeVmcnt(Version, Waitcnt, Vmcnt);
|
|
Waitcnt = encodeExpcnt(Version, Waitcnt, Expcnt);
|
|
Waitcnt = encodeLgkmcnt(Version, Waitcnt, Lgkmcnt);
|
|
return Waitcnt;
|
|
}
|
|
|
|
unsigned encodeWaitcnt(const IsaVersion &Version, const Waitcnt &Decoded) {
|
|
return encodeWaitcnt(Version, Decoded.VmCnt, Decoded.ExpCnt, Decoded.LgkmCnt);
|
|
}
|
|
|
|
unsigned getInitialPSInputAddr(const Function &F) {
|
|
return getIntegerAttribute(F, "InitialPSInputAddr", 0);
|
|
}
|
|
|
|
bool isShader(CallingConv::ID cc) {
|
|
switch(cc) {
|
|
case CallingConv::AMDGPU_VS:
|
|
case CallingConv::AMDGPU_LS:
|
|
case CallingConv::AMDGPU_HS:
|
|
case CallingConv::AMDGPU_ES:
|
|
case CallingConv::AMDGPU_GS:
|
|
case CallingConv::AMDGPU_PS:
|
|
case CallingConv::AMDGPU_CS:
|
|
return true;
|
|
default:
|
|
return false;
|
|
}
|
|
}
|
|
|
|
bool isCompute(CallingConv::ID cc) {
|
|
return !isShader(cc) || cc == CallingConv::AMDGPU_CS;
|
|
}
|
|
|
|
bool isEntryFunctionCC(CallingConv::ID CC) {
|
|
switch (CC) {
|
|
case CallingConv::AMDGPU_KERNEL:
|
|
case CallingConv::SPIR_KERNEL:
|
|
case CallingConv::AMDGPU_VS:
|
|
case CallingConv::AMDGPU_GS:
|
|
case CallingConv::AMDGPU_PS:
|
|
case CallingConv::AMDGPU_CS:
|
|
case CallingConv::AMDGPU_ES:
|
|
case CallingConv::AMDGPU_HS:
|
|
case CallingConv::AMDGPU_LS:
|
|
return true;
|
|
default:
|
|
return false;
|
|
}
|
|
}
|
|
|
|
bool hasXNACK(const MCSubtargetInfo &STI) {
|
|
return STI.getFeatureBits()[AMDGPU::FeatureXNACK];
|
|
}
|
|
|
|
bool hasSRAMECC(const MCSubtargetInfo &STI) {
|
|
return STI.getFeatureBits()[AMDGPU::FeatureSRAMECC];
|
|
}
|
|
|
|
bool hasMIMG_R128(const MCSubtargetInfo &STI) {
|
|
return STI.getFeatureBits()[AMDGPU::FeatureMIMG_R128];
|
|
}
|
|
|
|
bool hasPackedD16(const MCSubtargetInfo &STI) {
|
|
return !STI.getFeatureBits()[AMDGPU::FeatureUnpackedD16VMem];
|
|
}
|
|
|
|
bool isSI(const MCSubtargetInfo &STI) {
|
|
return STI.getFeatureBits()[AMDGPU::FeatureSouthernIslands];
|
|
}
|
|
|
|
bool isCI(const MCSubtargetInfo &STI) {
|
|
return STI.getFeatureBits()[AMDGPU::FeatureSeaIslands];
|
|
}
|
|
|
|
bool isVI(const MCSubtargetInfo &STI) {
|
|
return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands];
|
|
}
|
|
|
|
bool isGFX9(const MCSubtargetInfo &STI) {
|
|
return STI.getFeatureBits()[AMDGPU::FeatureGFX9];
|
|
}
|
|
|
|
bool isGCN3Encoding(const MCSubtargetInfo &STI) {
|
|
return STI.getFeatureBits()[AMDGPU::FeatureGCN3Encoding];
|
|
}
|
|
|
|
bool isSGPR(unsigned Reg, const MCRegisterInfo* TRI) {
|
|
const MCRegisterClass SGPRClass = TRI->getRegClass(AMDGPU::SReg_32RegClassID);
|
|
const unsigned FirstSubReg = TRI->getSubReg(Reg, 1);
|
|
return SGPRClass.contains(FirstSubReg != 0 ? FirstSubReg : Reg) ||
|
|
Reg == AMDGPU::SCC;
|
|
}
|
|
|
|
bool isRegIntersect(unsigned Reg0, unsigned Reg1, const MCRegisterInfo* TRI) {
|
|
for (MCRegAliasIterator R(Reg0, TRI, true); R.isValid(); ++R) {
|
|
if (*R == Reg1) return true;
|
|
}
|
|
return false;
|
|
}
|
|
|
|
#define MAP_REG2REG \
|
|
using namespace AMDGPU; \
|
|
switch(Reg) { \
|
|
default: return Reg; \
|
|
CASE_CI_VI(FLAT_SCR) \
|
|
CASE_CI_VI(FLAT_SCR_LO) \
|
|
CASE_CI_VI(FLAT_SCR_HI) \
|
|
CASE_VI_GFX9(TTMP0) \
|
|
CASE_VI_GFX9(TTMP1) \
|
|
CASE_VI_GFX9(TTMP2) \
|
|
CASE_VI_GFX9(TTMP3) \
|
|
CASE_VI_GFX9(TTMP4) \
|
|
CASE_VI_GFX9(TTMP5) \
|
|
CASE_VI_GFX9(TTMP6) \
|
|
CASE_VI_GFX9(TTMP7) \
|
|
CASE_VI_GFX9(TTMP8) \
|
|
CASE_VI_GFX9(TTMP9) \
|
|
CASE_VI_GFX9(TTMP10) \
|
|
CASE_VI_GFX9(TTMP11) \
|
|
CASE_VI_GFX9(TTMP12) \
|
|
CASE_VI_GFX9(TTMP13) \
|
|
CASE_VI_GFX9(TTMP14) \
|
|
CASE_VI_GFX9(TTMP15) \
|
|
CASE_VI_GFX9(TTMP0_TTMP1) \
|
|
CASE_VI_GFX9(TTMP2_TTMP3) \
|
|
CASE_VI_GFX9(TTMP4_TTMP5) \
|
|
CASE_VI_GFX9(TTMP6_TTMP7) \
|
|
CASE_VI_GFX9(TTMP8_TTMP9) \
|
|
CASE_VI_GFX9(TTMP10_TTMP11) \
|
|
CASE_VI_GFX9(TTMP12_TTMP13) \
|
|
CASE_VI_GFX9(TTMP14_TTMP15) \
|
|
CASE_VI_GFX9(TTMP0_TTMP1_TTMP2_TTMP3) \
|
|
CASE_VI_GFX9(TTMP4_TTMP5_TTMP6_TTMP7) \
|
|
CASE_VI_GFX9(TTMP8_TTMP9_TTMP10_TTMP11) \
|
|
CASE_VI_GFX9(TTMP12_TTMP13_TTMP14_TTMP15) \
|
|
CASE_VI_GFX9(TTMP0_TTMP1_TTMP2_TTMP3_TTMP4_TTMP5_TTMP6_TTMP7) \
|
|
CASE_VI_GFX9(TTMP4_TTMP5_TTMP6_TTMP7_TTMP8_TTMP9_TTMP10_TTMP11) \
|
|
CASE_VI_GFX9(TTMP8_TTMP9_TTMP10_TTMP11_TTMP12_TTMP13_TTMP14_TTMP15) \
|
|
CASE_VI_GFX9(TTMP0_TTMP1_TTMP2_TTMP3_TTMP4_TTMP5_TTMP6_TTMP7_TTMP8_TTMP9_TTMP10_TTMP11_TTMP12_TTMP13_TTMP14_TTMP15) \
|
|
}
|
|
|
|
#define CASE_CI_VI(node) \
|
|
assert(!isSI(STI)); \
|
|
case node: return isCI(STI) ? node##_ci : node##_vi;
|
|
|
|
#define CASE_VI_GFX9(node) \
|
|
case node: return isGFX9(STI) ? node##_gfx9 : node##_vi;
|
|
|
|
unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI) {
|
|
if (STI.getTargetTriple().getArch() == Triple::r600)
|
|
return Reg;
|
|
MAP_REG2REG
|
|
}
|
|
|
|
#undef CASE_CI_VI
|
|
#undef CASE_VI_GFX9
|
|
|
|
#define CASE_CI_VI(node) case node##_ci: case node##_vi: return node;
|
|
#define CASE_VI_GFX9(node) case node##_vi: case node##_gfx9: return node;
|
|
|
|
unsigned mc2PseudoReg(unsigned Reg) {
|
|
MAP_REG2REG
|
|
}
|
|
|
|
#undef CASE_CI_VI
|
|
#undef CASE_VI_GFX9
|
|
#undef MAP_REG2REG
|
|
|
|
bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo) {
|
|
assert(OpNo < Desc.NumOperands);
|
|
unsigned OpType = Desc.OpInfo[OpNo].OperandType;
|
|
return OpType >= AMDGPU::OPERAND_SRC_FIRST &&
|
|
OpType <= AMDGPU::OPERAND_SRC_LAST;
|
|
}
|
|
|
|
bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo) {
|
|
assert(OpNo < Desc.NumOperands);
|
|
unsigned OpType = Desc.OpInfo[OpNo].OperandType;
|
|
switch (OpType) {
|
|
case AMDGPU::OPERAND_REG_IMM_FP32:
|
|
case AMDGPU::OPERAND_REG_IMM_FP64:
|
|
case AMDGPU::OPERAND_REG_IMM_FP16:
|
|
case AMDGPU::OPERAND_REG_INLINE_C_FP32:
|
|
case AMDGPU::OPERAND_REG_INLINE_C_FP64:
|
|
case AMDGPU::OPERAND_REG_INLINE_C_FP16:
|
|
case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:
|
|
return true;
|
|
default:
|
|
return false;
|
|
}
|
|
}
|
|
|
|
bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo) {
|
|
assert(OpNo < Desc.NumOperands);
|
|
unsigned OpType = Desc.OpInfo[OpNo].OperandType;
|
|
return OpType >= AMDGPU::OPERAND_REG_INLINE_C_FIRST &&
|
|
OpType <= AMDGPU::OPERAND_REG_INLINE_C_LAST;
|
|
}
|
|
|
|
// Avoid using MCRegisterClass::getSize, since that function will go away
|
|
// (move from MC* level to Target* level). Return size in bits.
|
|
unsigned getRegBitWidth(unsigned RCID) {
|
|
switch (RCID) {
|
|
case AMDGPU::SGPR_32RegClassID:
|
|
case AMDGPU::VGPR_32RegClassID:
|
|
case AMDGPU::VS_32RegClassID:
|
|
case AMDGPU::SReg_32RegClassID:
|
|
case AMDGPU::SReg_32_XM0RegClassID:
|
|
return 32;
|
|
case AMDGPU::SGPR_64RegClassID:
|
|
case AMDGPU::VS_64RegClassID:
|
|
case AMDGPU::SReg_64RegClassID:
|
|
case AMDGPU::VReg_64RegClassID:
|
|
case AMDGPU::SReg_64_XEXECRegClassID:
|
|
return 64;
|
|
case AMDGPU::VReg_96RegClassID:
|
|
return 96;
|
|
case AMDGPU::SGPR_128RegClassID:
|
|
case AMDGPU::SReg_128RegClassID:
|
|
case AMDGPU::VReg_128RegClassID:
|
|
return 128;
|
|
case AMDGPU::SReg_256RegClassID:
|
|
case AMDGPU::VReg_256RegClassID:
|
|
return 256;
|
|
case AMDGPU::SReg_512RegClassID:
|
|
case AMDGPU::VReg_512RegClassID:
|
|
return 512;
|
|
default:
|
|
llvm_unreachable("Unexpected register class");
|
|
}
|
|
}
|
|
|
|
unsigned getRegBitWidth(const MCRegisterClass &RC) {
|
|
return getRegBitWidth(RC.getID());
|
|
}
|
|
|
|
unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc,
|
|
unsigned OpNo) {
|
|
assert(OpNo < Desc.NumOperands);
|
|
unsigned RCID = Desc.OpInfo[OpNo].RegClass;
|
|
return getRegBitWidth(MRI->getRegClass(RCID)) / 8;
|
|
}
|
|
|
|
bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi) {
|
|
if (Literal >= -16 && Literal <= 64)
|
|
return true;
|
|
|
|
uint64_t Val = static_cast<uint64_t>(Literal);
|
|
return (Val == DoubleToBits(0.0)) ||
|
|
(Val == DoubleToBits(1.0)) ||
|
|
(Val == DoubleToBits(-1.0)) ||
|
|
(Val == DoubleToBits(0.5)) ||
|
|
(Val == DoubleToBits(-0.5)) ||
|
|
(Val == DoubleToBits(2.0)) ||
|
|
(Val == DoubleToBits(-2.0)) ||
|
|
(Val == DoubleToBits(4.0)) ||
|
|
(Val == DoubleToBits(-4.0)) ||
|
|
(Val == 0x3fc45f306dc9c882 && HasInv2Pi);
|
|
}
|
|
|
|
bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi) {
|
|
if (Literal >= -16 && Literal <= 64)
|
|
return true;
|
|
|
|
// The actual type of the operand does not seem to matter as long
|
|
// as the bits match one of the inline immediate values. For example:
|
|
//
|
|
// -nan has the hexadecimal encoding of 0xfffffffe which is -2 in decimal,
|
|
// so it is a legal inline immediate.
|
|
//
|
|
// 1065353216 has the hexadecimal encoding 0x3f800000 which is 1.0f in
|
|
// floating-point, so it is a legal inline immediate.
|
|
|
|
uint32_t Val = static_cast<uint32_t>(Literal);
|
|
return (Val == FloatToBits(0.0f)) ||
|
|
(Val == FloatToBits(1.0f)) ||
|
|
(Val == FloatToBits(-1.0f)) ||
|
|
(Val == FloatToBits(0.5f)) ||
|
|
(Val == FloatToBits(-0.5f)) ||
|
|
(Val == FloatToBits(2.0f)) ||
|
|
(Val == FloatToBits(-2.0f)) ||
|
|
(Val == FloatToBits(4.0f)) ||
|
|
(Val == FloatToBits(-4.0f)) ||
|
|
(Val == 0x3e22f983 && HasInv2Pi);
|
|
}
|
|
|
|
bool isInlinableLiteral16(int16_t Literal, bool HasInv2Pi) {
|
|
if (!HasInv2Pi)
|
|
return false;
|
|
|
|
if (Literal >= -16 && Literal <= 64)
|
|
return true;
|
|
|
|
uint16_t Val = static_cast<uint16_t>(Literal);
|
|
return Val == 0x3C00 || // 1.0
|
|
Val == 0xBC00 || // -1.0
|
|
Val == 0x3800 || // 0.5
|
|
Val == 0xB800 || // -0.5
|
|
Val == 0x4000 || // 2.0
|
|
Val == 0xC000 || // -2.0
|
|
Val == 0x4400 || // 4.0
|
|
Val == 0xC400 || // -4.0
|
|
Val == 0x3118; // 1/2pi
|
|
}
|
|
|
|
bool isInlinableLiteralV216(int32_t Literal, bool HasInv2Pi) {
|
|
assert(HasInv2Pi);
|
|
|
|
int16_t Lo16 = static_cast<int16_t>(Literal);
|
|
int16_t Hi16 = static_cast<int16_t>(Literal >> 16);
|
|
return Lo16 == Hi16 && isInlinableLiteral16(Lo16, HasInv2Pi);
|
|
}
|
|
|
|
bool isArgPassedInSGPR(const Argument *A) {
|
|
const Function *F = A->getParent();
|
|
|
|
// Arguments to compute shaders are never a source of divergence.
|
|
CallingConv::ID CC = F->getCallingConv();
|
|
switch (CC) {
|
|
case CallingConv::AMDGPU_KERNEL:
|
|
case CallingConv::SPIR_KERNEL:
|
|
return true;
|
|
case CallingConv::AMDGPU_VS:
|
|
case CallingConv::AMDGPU_LS:
|
|
case CallingConv::AMDGPU_HS:
|
|
case CallingConv::AMDGPU_ES:
|
|
case CallingConv::AMDGPU_GS:
|
|
case CallingConv::AMDGPU_PS:
|
|
case CallingConv::AMDGPU_CS:
|
|
// For non-compute shaders, SGPR inputs are marked with either inreg or byval.
|
|
// Everything else is in VGPRs.
|
|
return F->getAttributes().hasParamAttribute(A->getArgNo(), Attribute::InReg) ||
|
|
F->getAttributes().hasParamAttribute(A->getArgNo(), Attribute::ByVal);
|
|
default:
|
|
// TODO: Should calls support inreg for SGPR inputs?
|
|
return false;
|
|
}
|
|
}
|
|
|
|
int64_t getSMRDEncodedOffset(const MCSubtargetInfo &ST, int64_t ByteOffset) {
|
|
if (isGCN3Encoding(ST))
|
|
return ByteOffset;
|
|
return ByteOffset >> 2;
|
|
}
|
|
|
|
bool isLegalSMRDImmOffset(const MCSubtargetInfo &ST, int64_t ByteOffset) {
|
|
int64_t EncodedOffset = getSMRDEncodedOffset(ST, ByteOffset);
|
|
return isGCN3Encoding(ST) ?
|
|
isUInt<20>(EncodedOffset) : isUInt<8>(EncodedOffset);
|
|
}
|
|
|
|
// Given Imm, split it into the values to put into the SOffset and ImmOffset
|
|
// fields in an MUBUF instruction. Return false if it is not possible (due to a
|
|
// hardware bug needing a workaround).
|
|
//
|
|
// The required alignment ensures that individual address components remain
|
|
// aligned if they are aligned to begin with. It also ensures that additional
|
|
// offsets within the given alignment can be added to the resulting ImmOffset.
|
|
bool splitMUBUFOffset(uint32_t Imm, uint32_t &SOffset, uint32_t &ImmOffset,
|
|
const GCNSubtarget *Subtarget, uint32_t Align) {
|
|
const uint32_t MaxImm = alignDown(4095, Align);
|
|
uint32_t Overflow = 0;
|
|
|
|
if (Imm > MaxImm) {
|
|
if (Imm <= MaxImm + 64) {
|
|
// Use an SOffset inline constant for 4..64
|
|
Overflow = Imm - MaxImm;
|
|
Imm = MaxImm;
|
|
} else {
|
|
// Try to keep the same value in SOffset for adjacent loads, so that
|
|
// the corresponding register contents can be re-used.
|
|
//
|
|
// Load values with all low-bits (except for alignment bits) set into
|
|
// SOffset, so that a larger range of values can be covered using
|
|
// s_movk_i32.
|
|
//
|
|
// Atomic operations fail to work correctly when individual address
|
|
// components are unaligned, even if their sum is aligned.
|
|
uint32_t High = (Imm + Align) & ~4095;
|
|
uint32_t Low = (Imm + Align) & 4095;
|
|
Imm = Low;
|
|
Overflow = High - Align;
|
|
}
|
|
}
|
|
|
|
// There is a hardware bug in SI and CI which prevents address clamping in
|
|
// MUBUF instructions from working correctly with SOffsets. The immediate
|
|
// offset is unaffected.
|
|
if (Overflow > 0 &&
|
|
Subtarget->getGeneration() <= AMDGPUSubtarget::SEA_ISLANDS)
|
|
return false;
|
|
|
|
ImmOffset = Imm;
|
|
SOffset = Overflow;
|
|
return true;
|
|
}
|
|
|
|
namespace {
|
|
|
|
struct SourceOfDivergence {
|
|
unsigned Intr;
|
|
};
|
|
const SourceOfDivergence *lookupSourceOfDivergence(unsigned Intr);
|
|
|
|
#define GET_SourcesOfDivergence_IMPL
|
|
#include "AMDGPUGenSearchableTables.inc"
|
|
|
|
} // end anonymous namespace
|
|
|
|
bool isIntrinsicSourceOfDivergence(unsigned IntrID) {
|
|
return lookupSourceOfDivergence(IntrID);
|
|
}
|
|
} // namespace AMDGPU
|
|
} // namespace llvm
|