..
AsmParser
[RISCV] Support ABI checking with per function target-features
2020-01-22 08:12:28 -08:00
Disassembler
CMake: Make most target symbols hidden by default
2020-01-14 19:46:52 -08:00
MCTargetDesc
[RISCV] Fix evaluating %pcrel_lo against global and weak symbols
2020-01-23 02:05:48 +00:00
TargetInfo
CMake: Make most target symbols hidden by default
2020-01-14 19:46:52 -08:00
Utils
[RISCV] Support ABI checking with per function target-features
2020-01-22 08:12:28 -08:00
CMakeLists.txt
LLVMBuild.txt
RISCV.h
RISCV.td
[RISCV] Scheduler description for the Rocket core
2020-01-23 19:36:47 -06:00
RISCVAsmPrinter.cpp
CMake: Make most target symbols hidden by default
2020-01-14 19:46:52 -08:00
RISCVCallingConv.td
RISCVCallLowering.cpp
RISCVCallLowering.h
RISCVExpandPseudoInsts.cpp
RISCVFrameLowering.cpp
[RISCV] Allow shrink wrapping for RISC-V
2020-01-14 18:59:11 +00:00
RISCVFrameLowering.h
RISCVInstrFormats.td
[RISCV] Scheduler description for the Rocket core
2020-01-23 19:36:47 -06:00
RISCVInstrFormatsC.td
RISCVInstrInfo.cpp
Update spelling of {analyze,insert,remove}Branch in strings and comments
2020-01-21 10:15:38 -06:00
RISCVInstrInfo.h
[RISCV] Enable the machine outliner for RISC-V
2019-12-19 16:41:53 +00:00
RISCVInstrInfo.td
[RISCV] Scheduler description for the Rocket core
2020-01-23 19:36:47 -06:00
RISCVInstrInfoA.td
[RISCV] Scheduler description for the Rocket core
2020-01-23 19:36:47 -06:00
RISCVInstrInfoC.td
[RISCV] Scheduler description for the Rocket core
2020-01-23 19:36:47 -06:00
RISCVInstrInfoD.td
[RISCV] Scheduler description for the Rocket core
2020-01-23 19:36:47 -06:00
RISCVInstrInfoF.td
[RISCV] Scheduler description for the Rocket core
2020-01-23 19:36:47 -06:00
RISCVInstrInfoM.td
[RISCV] Scheduler description for the Rocket core
2020-01-23 19:36:47 -06:00
RISCVInstructionSelector.cpp
RISCVISelDAGToDAG.cpp
[SelectionDAG] Disallow indirect "i" constraint
2019-12-29 16:50:42 -08:00
RISCVISelLowering.cpp
[RISCV] Support ABI checking with per function target-features
2020-01-22 08:12:28 -08:00
RISCVISelLowering.h
CodeGen: Use LLT instead of EVT in getRegisterByName
2020-01-09 17:37:52 -05:00
RISCVLegalizerInfo.cpp
RISCVLegalizerInfo.h
RISCVMachineFunctionInfo.h
RISCVMCInstLower.cpp
RISCVMergeBaseOffset.cpp
RISCVRegisterBankInfo.cpp
RISCVRegisterBankInfo.h
RISCVRegisterBanks.td
RISCVRegisterInfo.cpp
RISCVRegisterInfo.h
[TargetRegisterInfo] Default trackLivenessAfterRegAlloc() to true
2020-01-19 14:20:37 -08:00
RISCVRegisterInfo.td
RISCVSchedRocket32.td
[RISCV] Scheduler description for the Rocket core
2020-01-23 19:36:47 -06:00
RISCVSchedRocket64.td
[RISCV] Scheduler description for the Rocket core
2020-01-23 19:36:47 -06:00
RISCVSchedule.td
[RISCV] Scheduler description for the Rocket core
2020-01-23 19:36:47 -06:00
RISCVSubtarget.cpp
RISCVSubtarget.h
RISCVSystemOperands.td
RISCVTargetMachine.cpp
[RISCV] Check the target-abi module flag matches the option
2020-01-21 07:32:12 -08:00
RISCVTargetMachine.h
[RISCV] Add subtargets initialized with target feature
2019-12-17 09:34:01 -08:00
RISCVTargetObjectFile.cpp
Revert "Honor -fuse-init-array when os is not specified on x86"
2019-12-17 07:36:59 -08:00
RISCVTargetObjectFile.h
RISCVTargetTransformInfo.cpp
Rename TTI::getIntImmCost for instructions and intrinsics
2019-12-11 18:00:20 -08:00
RISCVTargetTransformInfo.h
Rename TTI::getIntImmCost for instructions and intrinsics
2019-12-11 18:00:20 -08:00
