mirror of
https://github.com/Gericom/teak-llvm.git
synced 2025-06-19 03:25:54 -04:00
3da44a85b7
Fixed invalid mpy instruction being generated Fixed byte order of 32 bit values when emitted to the elf file Support for addv/subv to modify 16 bit registers directly Support for move 8bit immediate Support for tst0 instruction Support for directly adding p0 to an ab register after mpy Support for 8 bit immediate multiply Support for modr instruction Support for post increase/decrement for loads and stores Use copy instruction for a to a register moves
81 lines
3.3 KiB
C++
81 lines
3.3 KiB
C++
//===-- TeakRegisterInfo.h - Teak Register Information Impl ---*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Teak implementation of the MRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef TEAKREGISTERINFO_H
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#define TEAKREGISTERINFO_H
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#define GET_REGINFO_HEADER
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#include "TeakGenRegisterInfo.inc"
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namespace llvm {
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struct TeakRegisterInfo : public TeakGenRegisterInfo {
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public:
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TeakRegisterInfo();
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/// Code Generation virtual methods...
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const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const
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override;
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const uint32_t *getCallPreservedMask(const MachineFunction &MF,
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CallingConv::ID CC) const override;
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BitVector getReservedRegs(const MachineFunction &MF) const override;
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const TargetRegisterClass* getLargestLegalSuperClass(
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const TargetRegisterClass* RC, const MachineFunction &MF) const override;
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const TargetRegisterClass* getPointerRegClass(
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const MachineFunction &MF, unsigned Kind) const override;
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bool requiresRegisterScavenging(const MachineFunction &MF) const override;
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bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override;
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bool useFPForScavengingIndex(const MachineFunction &MF) const override;
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bool requiresFrameIndexScavenging(const MachineFunction &MF) const override;
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bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override;
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void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
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unsigned FIOperandNum,
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RegScavenger *RS = nullptr) const override;
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unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override;
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// Debug information queries.
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Register getFrameRegister(const MachineFunction &MF) const override;
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virtual bool isFrameOffsetLegal(const MachineInstr* MI, unsigned BaseReg, int64_t Offset) const override;
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virtual bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override;
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virtual int64_t getFrameIndexInstrOffset(const MachineInstr* MI, int Idx) const override;
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virtual void materializeFrameBaseRegister(MachineBasicBlock *MBB, unsigned BaseReg,
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int FrameIdx, int64_t Offset) const override;
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virtual void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, int64_t Offset) const override;
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virtual bool shouldCoalesce(MachineInstr *MI,
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const TargetRegisterClass *SrcRC,
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unsigned SubReg,
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const TargetRegisterClass *DstRC,
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unsigned DstSubReg,
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const TargetRegisterClass *NewRC,
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LiveIntervals &LIS) const override;
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virtual const TargetRegisterClass* getCrossCopyRegClass(const TargetRegisterClass* RC) const override;
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};
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} // end namespace llvm
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#endif |