mirror of
https://github.com/Gericom/teak-llvm.git
synced 2025-06-19 03:25:54 -04:00
3da44a85b7
Fixed invalid mpy instruction being generated Fixed byte order of 32 bit values when emitted to the elf file Support for addv/subv to modify 16 bit registers directly Support for move 8bit immediate Support for tst0 instruction Support for directly adding p0 to an ab register after mpy Support for 8 bit immediate multiply Support for modr instruction Support for post increase/decrement for loads and stores Use copy instruction for a to a register moves
119 lines
4.6 KiB
TableGen
119 lines
4.6 KiB
TableGen
//===-- TeakOperators.td - Teak-specific operators ------*- tblgen-*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Type profiles
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//===----------------------------------------------------------------------===//
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// def MoveImm32Ty : SDTypeProfile<1, 1, [
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// SDTCisSameAs<0, 1>, SDTCisInt<0>
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// ]>;
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def SDT_TeakCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i16>, SDTCisVT<1, i16> ]>;
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def SDT_TeakCallSeqEnd : SDCallSeqEnd<[
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SDTCisVT<0, i16>, SDTCisVT<1, i16>
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]>;
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def TeakRetFlag : SDNode<"TeakISD::RET_FLAG", SDTNone,
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[SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
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def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_TeakCallSeqStart,
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[SDNPHasChain, SDNPOutGlue]>;
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def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_TeakCallSeqEnd,
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[SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
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def SDT_TeakCall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
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def SDT_TeakCmpICC : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>;
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def TeakCmpICC : SDNode<"TeakISD::CMPICC", SDT_TeakCmpICC, [SDNPOutGlue]>;
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def SDT_TeakCmpzICC : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>;
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def TeakCmpzICC : SDNode<"TeakISD::CMPZICC", SDT_TeakCmpzICC, [SDNPOutGlue]>;
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def SDT_TeakSelectCC : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i40>]>;
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def TeakSelectICC : SDNode<"TeakISD::SELECT_ICC", SDT_TeakSelectCC, [SDNPInGlue]>;
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// Operand for printing out a condition code.
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let PrintMethod = "printCondCode" in
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def CCOp : Operand<i40>;
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def SDT_TeakBRCC : SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i40>]>;
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def TeakBRICC : SDNode<"TeakISD::BRICC", SDT_TeakBRCC, [SDNPHasChain, SDNPInGlue]>;
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// //===----------------------------------------------------------------------===//
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// // Custom SDNodes.
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// //===----------------------------------------------------------------------===//
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// def load_sym : SDNode<"TeakISD::LOAD_SYM", SDTIntUnaryOp>;
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// def movei32 : SDNode<"TeakISD::MOVEi32", MoveImm32Ty>;
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def teak_call
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: SDNode<"TeakISD::CALL", SDT_TeakCall,
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[ SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic ]>;
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def memsrc : Operand<i16> {
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let MIOperandInfo = (ops FP, i16imm);
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let PrintMethod = "printAddrModeMemSrc";
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let EncoderMethod = "getMemSrcValue";
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}
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def addr : ComplexPattern<iPTR, 2, "SelectAddr", [frameindex], []>;
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def SDT_TeakWrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
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def TeakWrapper : SDNode<"TeakISD::WRAPPER", SDT_TeakWrapper>;
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def SDT_TeakShift : SDTypeProfile<1, 2, [SDTCisVT<0, i40>, SDTCisVT<1, i40>, SDTCisInt<2>]>;
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def TeakShiftArith : SDNode<"TeakISD::SHIFT_ARITH", SDT_TeakShift>;
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def TeakShiftLogic : SDNode<"TeakISD::SHIFT_LOGIC", SDT_TeakShift>;
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def SDT_TeakAnd : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<1, 0>, SDTCisSameAs<2, 0>]>;
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def TeakAnd : SDNode<"TeakISD::AND", SDT_TeakAnd>;
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def SDT_TeakOr : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<1, 0>, SDTCisSameAs<2, 0>]>;
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def TeakOr : SDNode<"TeakISD::OR", SDT_TeakOr>;
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def SDT_TeakXor : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<1, 0>, SDTCisSameAs<2, 0>]>;
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def TeakXor : SDNode<"TeakISD::XOR", SDT_TeakXor>;
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def SDT_TeakMpy : SDTypeProfile<1, 2, [SDTCisVT<0, i40>, SDTCisVT<1, i16>, SDTCisVT<2, i16>]>;
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def TeakMpy : SDNode<"TeakISD::MPY", SDT_TeakMpy>;
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// //===----------------------------------------------------------------------===//
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// // Operand Definitions.
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// //===----------------------------------------------------------------------===//
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// def bl_target : Operand<i32>;
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// def b_target : Operand<OtherVT>;
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// def cc_val : Operand<i32> {
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// let PrintMethod = "printCondCode";
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// }
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// def memsrc : Operand<i32> {
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// let MIOperandInfo = (ops GRRegs, i32imm);
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// let PrintMethod = "printAddrModeMemSrc";
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// let EncoderMethod = "getMemSrcValue";
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// }
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// def i32imm_lo : Operand<i32>, ImmLeaf<i32, [{
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// return Imm >= 0 && Imm < 65536;
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// }]>;
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// def Teakimm8 : Operand<i32>, ImmLeaf<i32, [{
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// return Imm >= 0 && Imm < 256;
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// }]>;
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// //===----------------------------------------------------------------------===//
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// // Complex Pattern Definitions.
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// //===----------------------------------------------------------------------===//
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// def addr : ComplexPattern<iPTR, 2, "SelectAddr", [], []>;
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