mirror of
https://github.com/Gericom/teak-llvm.git
synced 2025-06-19 03:25:54 -04:00
3da44a85b7
Fixed invalid mpy instruction being generated Fixed byte order of 32 bit values when emitted to the elf file Support for addv/subv to modify 16 bit registers directly Support for move 8bit immediate Support for tst0 instruction Support for directly adding p0 to an ab register after mpy Support for 8 bit immediate multiply Support for modr instruction Support for post increase/decrement for loads and stores Use copy instruction for a to a register moves
106 lines
5.0 KiB
C++
106 lines
5.0 KiB
C++
//===-- TeakInstrInfo.h - Teak Instruction Information --------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Teak implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef TEAKINSTRUCTIONINFO_H
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#define TEAKINSTRUCTIONINFO_H
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#include "TeakRegisterInfo.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#define GET_INSTRINFO_HEADER
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#include "TeakGenInstrInfo.inc"
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namespace llvm {
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class TeakInstrInfo : public TeakGenInstrInfo {
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const TeakRegisterInfo RI;
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virtual void anchor();
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void makeRnRegDisplacement(MachineBasicBlock& mbb, MachineInstr& mi, const DebugLoc& dl, Register reg, signed short offset) const;
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public:
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TeakInstrInfo();
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/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
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/// such, whenever a client has an instance of instruction info, it should
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/// always be able to get register info as well (through this method).
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///
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const TeakRegisterInfo &getRegisterInfo() const { return RI; }
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/// isLoadFromStackSlot - If the specified machine instruction is a direct
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/// load from a stack slot, return the virtual or physical register number of
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/// the destination along with the FrameIndex of the loaded stack slot. If
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/// not, return 0. This predicate must return 0 if the instruction has
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// /// any side effects other than loading from the stack slot.
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// virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
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// int &FrameIndex) const override;
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// /// isStoreToStackSlot - If the specified machine instruction is a direct
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// /// store to a stack slot, return the virtual or physical register number of
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// /// the source reg along with the FrameIndex of the loaded stack slot. If
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// /// not, return 0. This predicate must return 0 if the instruction has
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// /// any side effects other than storing to the stack slot.
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// virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
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// int &FrameIndex) const override;
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virtual bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify = false) const override;
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virtual unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved = nullptr) const override;
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unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
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const DebugLoc &DL,
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int *BytesAdded = nullptr) const override;
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virtual bool reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
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virtual bool isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const override;
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virtual MachineBasicBlock* getBranchDestBlock(const MachineInstr &MI) const override;
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virtual unsigned insertIndirectBranch(MachineBasicBlock &MBB, MachineBasicBlock &NewDestBB,
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const DebugLoc &DL, int64_t BrOffset = 0, RegScavenger *RS = nullptr) const override;
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virtual unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
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virtual void copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I, const DebugLoc &DL,
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MCRegister DestReg, MCRegister SrcReg,
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bool KillSrc) const override;
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virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned SrcReg, bool isKill, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const
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override;
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virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const
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override;
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virtual bool isPredicated(const MachineInstr &MI) const override;
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virtual bool PredicateInstruction(MachineInstr &MI, ArrayRef<MachineOperand> Pred) const override;
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virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const;
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virtual bool isProfitableToIfCvt(MachineBasicBlock &TBB, unsigned TCycles, unsigned TExtra, MachineBasicBlock &FBB, unsigned FCycles, unsigned FExtra, BranchProbability Probability) const;
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virtual bool expandPostRAPseudo(MachineInstr &MI) const
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override;
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};
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}
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#endif |