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391a98afd5
When a block has no terminator instructions, getFirstTerminator() returns end(), which can't be used in dominance checks. Check dominance for phi operands separately. Also, remove some bits from WebAssemblyRegStackify.cpp that were causing trouble on the same testcase; they were left behind from an earlier experiment. Differential Revision: http://reviews.llvm.org/D15210 llvm-svn: 254662
118 lines
4.1 KiB
C++
118 lines
4.1 KiB
C++
//===-- WebAssemblyStoreResults.cpp - Optimize using store result values --===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// \brief This file implements an optimization pass using store result values.
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///
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/// WebAssembly's store instructions return the stored value. This is to enable
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/// an optimization wherein uses of the stored value can be replaced by uses of
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/// the store's result value, making the stored value register more likely to
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/// be single-use, thus more likely to be useful to register stackifying, and
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/// potentially also exposing the store to register stackifying. These both can
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/// reduce get_local/set_local traffic.
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///
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//===----------------------------------------------------------------------===//
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#include "WebAssembly.h"
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#include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
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#include "WebAssemblyMachineFunctionInfo.h"
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#include "WebAssemblySubtarget.h"
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#include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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#define DEBUG_TYPE "wasm-store-results"
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namespace {
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class WebAssemblyStoreResults final : public MachineFunctionPass {
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public:
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static char ID; // Pass identification, replacement for typeid
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WebAssemblyStoreResults() : MachineFunctionPass(ID) {}
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const char *getPassName() const override {
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return "WebAssembly Store Results";
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}
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.setPreservesCFG();
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AU.addRequired<MachineBlockFrequencyInfo>();
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AU.addPreserved<MachineBlockFrequencyInfo>();
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AU.addRequired<MachineDominatorTree>();
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AU.addPreserved<MachineDominatorTree>();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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private:
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};
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} // end anonymous namespace
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char WebAssemblyStoreResults::ID = 0;
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FunctionPass *llvm::createWebAssemblyStoreResults() {
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return new WebAssemblyStoreResults();
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}
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bool WebAssemblyStoreResults::runOnMachineFunction(MachineFunction &MF) {
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DEBUG({
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dbgs() << "********** Store Results **********\n"
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<< "********** Function: " << MF.getName() << '\n';
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});
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const MachineRegisterInfo &MRI = MF.getRegInfo();
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MachineDominatorTree &MDT = getAnalysis<MachineDominatorTree>();
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for (auto &MBB : MF) {
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DEBUG(dbgs() << "Basic Block: " << MBB.getName() << '\n');
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for (auto &MI : MBB)
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switch (MI.getOpcode()) {
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default:
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break;
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case WebAssembly::STORE8_I32:
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case WebAssembly::STORE16_I32:
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case WebAssembly::STORE8_I64:
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case WebAssembly::STORE16_I64:
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case WebAssembly::STORE32_I64:
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case WebAssembly::STORE_F32:
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case WebAssembly::STORE_F64:
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case WebAssembly::STORE_I32:
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case WebAssembly::STORE_I64:
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unsigned ToReg = MI.getOperand(0).getReg();
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unsigned FromReg = MI.getOperand(2).getReg();
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for (auto I = MRI.use_begin(FromReg), E = MRI.use_end(); I != E;) {
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MachineOperand &O = *I++;
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MachineInstr *Where = O.getParent();
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if (Where->getOpcode() == TargetOpcode::PHI) {
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// PHIs use their operands on their incoming CFG edges rather than
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// in their parent blocks. Get the basic block paired with this use
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// of FromReg and check that MI's block dominates it.
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MachineBasicBlock *Pred =
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Where->getOperand(&O - &Where->getOperand(0) + 1).getMBB();
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if (!MDT.dominates(&MBB, Pred))
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continue;
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} else {
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// For a non-PHI, check that MI dominates the instruction in the
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// normal way.
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if (&MI == Where || !MDT.dominates(&MI, Where))
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continue;
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}
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DEBUG(dbgs() << "Setting operand " << O << " in " << *Where
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<< " from " << MI << "\n");
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O.setReg(ToReg);
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}
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}
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}
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return true;
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}
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