teak-llvm/llvm/lib/CodeGen/SelectionDAG
2019-10-29 12:41:24 +00:00
..
CMakeLists.txt
DAGCombiner.cpp [DAGCombiner] widen any_ext of popcount based on target support 2019-10-28 10:07:12 -04:00
FastISel.cpp Recommit "Add a heap alloc site marker field to the ExtraInfo in MachineInstrs" 2019-10-28 16:59:32 -07:00
FunctionLoweringInfo.cpp Prune a LegacyDivergenceAnalysis and MachineLoopInfo include each 2019-10-19 01:31:09 +00:00
InstrEmitter.cpp [DebugInfo] Remove some users of DBG_VALUEs IsIndirect field 2019-10-15 10:46:24 +00:00
InstrEmitter.h
LegalizeDAG.cpp Prune Analysis includes from SelectionDAG.h 2019-10-19 01:07:48 +00:00
LegalizeFloatTypes.cpp [Codegen][ARM] Add float softening for cbrt 2019-10-28 11:08:55 +00:00
LegalizeIntegerTypes.cpp [LegalizeTypes] When promoting BITREVERSE/BSWAP don't take the shift amount into account when determining the shift amount VT. 2019-10-27 12:20:35 -07:00
LegalizeTypes.cpp [LegalizeTypes] Remove code for softening a float type to itself. 2019-09-12 05:55:14 +00:00
LegalizeTypes.h [Codegen][ARM] Add float softening for cbrt 2019-10-28 11:08:55 +00:00
LegalizeTypesGeneric.cpp [LegalizeTypes][X86] When splitting a vselect for type legalization, don't split a setcc condition if the setcc input is legal and vXi1 conditions are supported 2019-10-06 18:43:03 +00:00
LegalizeVectorOps.cpp Prune a LegacyDivergenceAnalysis and MachineLoopInfo include each 2019-10-19 01:31:09 +00:00
LegalizeVectorTypes.cpp [LegalizeTypes] Don't use PromoteTargetBoolean in WidenVecOp_SETCC. 2019-10-16 03:29:24 +00:00
LLVMBuild.txt
ResourcePriorityQueue.cpp
ScheduleDAGFast.cpp Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register as started by r367614. NFC 2019-08-01 23:27:28 +00:00
ScheduleDAGRRList.cpp [ScheduleDAG] When a node is cloned, add an edge between the nodes. 2019-10-04 19:51:40 +00:00
ScheduleDAGSDNodes.cpp Recommit "Add a heap alloc site marker field to the ExtraInfo in MachineInstrs" 2019-10-28 16:59:32 -07:00
ScheduleDAGSDNodes.h Prune Analysis includes from SelectionDAG.h 2019-10-19 01:07:48 +00:00
ScheduleDAGVLIW.cpp Prune Analysis includes from SelectionDAG.h 2019-10-19 01:07:48 +00:00
SDNodeDbgValue.h
SelectionDAG.cpp [AArch64][SVE] Implement masked load intrinsics 2019-10-28 10:06:14 +00:00
SelectionDAGAddressAnalysis.cpp Prune a LegacyDivergenceAnalysis and MachineLoopInfo include each 2019-10-19 01:31:09 +00:00
SelectionDAGBuilder.cpp Fix some spelling mistakes in comments. NFC 2019-10-29 12:41:24 +00:00
SelectionDAGBuilder.h [llvm] Migrate llvm::make_unique to std::make_unique 2019-08-15 15:54:37 +00:00
SelectionDAGDumper.cpp [AArch64][SVE] Add SPLAT_VECTOR ISD Node 2019-10-18 11:48:35 +00:00
SelectionDAGISel.cpp Prune a LegacyDivergenceAnalysis and MachineLoopInfo include each 2019-10-19 01:31:09 +00:00
SelectionDAGPrinter.cpp
SelectionDAGTargetInfo.cpp
StatepointLowering.cpp [Statepoints] Fix overalignment of loads in no-realign-stack functions 2019-08-02 20:17:37 +00:00
StatepointLowering.h
TargetLowering.cpp [TargetLowering] Add getBooleanContents contents check to "SETCC (SETCC), [0|1], [EQ|NE] -> SETCC" combine. 2019-10-27 10:07:15 -07:00