mirror of
https://github.com/Gericom/teak-llvm.git
synced 2025-06-27 15:28:53 -04:00
19f98c6a09
This patch corrects the maximum workgroups per CU if we have big workgroups (more than 128). This calculation contributes to the occupancy calculation in respect to LDS size. Differential Revision: https://reviews.llvm.org/D29974 llvm-svn: 295134
678 lines
21 KiB
C++
678 lines
21 KiB
C++
//===- AMDGPUBaseInfo.cpp - AMDGPU Base encoding information --------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPU.h"
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#include "AMDGPUBaseInfo.h"
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#include "SIDefines.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/ADT/Triple.h"
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#include "llvm/CodeGen/MachineMemOperand.h"
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#include "llvm/IR/Attributes.h"
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#include "llvm/IR/Constants.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/GlobalValue.h"
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#include "llvm/IR/Instruction.h"
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#include "llvm/IR/LLVMContext.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCInstrDesc.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCSectionELF.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/MC/SubtargetFeature.h"
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#include "llvm/Support/Casting.h"
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#include "llvm/Support/ELF.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/MathExtras.h"
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#include <algorithm>
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#include <cassert>
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#include <cstdint>
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#include <cstring>
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#include <utility>
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#define GET_SUBTARGETINFO_ENUM
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#include "AMDGPUGenSubtargetInfo.inc"
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#undef GET_SUBTARGETINFO_ENUM
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#define GET_REGINFO_ENUM
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#include "AMDGPUGenRegisterInfo.inc"
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#undef GET_REGINFO_ENUM
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#define GET_INSTRINFO_NAMED_OPS
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#define GET_INSTRINFO_ENUM
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#include "AMDGPUGenInstrInfo.inc"
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#undef GET_INSTRINFO_NAMED_OPS
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#undef GET_INSTRINFO_ENUM
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namespace {
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/// \returns Bit mask for given bit \p Shift and bit \p Width.
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unsigned getBitMask(unsigned Shift, unsigned Width) {
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return ((1 << Width) - 1) << Shift;
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}
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/// \brief Packs \p Src into \p Dst for given bit \p Shift and bit \p Width.
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///
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/// \returns Packed \p Dst.
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unsigned packBits(unsigned Src, unsigned Dst, unsigned Shift, unsigned Width) {
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Dst &= ~(1 << Shift) & ~getBitMask(Shift, Width);
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Dst |= (Src << Shift) & getBitMask(Shift, Width);
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return Dst;
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}
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/// \brief Unpacks bits from \p Src for given bit \p Shift and bit \p Width.
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///
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/// \returns Unpacked bits.
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unsigned unpackBits(unsigned Src, unsigned Shift, unsigned Width) {
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return (Src & getBitMask(Shift, Width)) >> Shift;
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}
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/// \returns Vmcnt bit shift.
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unsigned getVmcntBitShift() { return 0; }
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/// \returns Vmcnt bit width.
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unsigned getVmcntBitWidth() { return 4; }
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/// \returns Expcnt bit shift.
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unsigned getExpcntBitShift() { return 4; }
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/// \returns Expcnt bit width.
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unsigned getExpcntBitWidth() { return 3; }
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/// \returns Lgkmcnt bit shift.
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unsigned getLgkmcntBitShift() { return 8; }
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/// \returns Lgkmcnt bit width.
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unsigned getLgkmcntBitWidth() { return 4; }
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} // end namespace anonymous
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namespace llvm {
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namespace AMDGPU {
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namespace IsaInfo {
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IsaVersion getIsaVersion(const FeatureBitset &Features) {
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// CI.
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if (Features.test(FeatureISAVersion7_0_0))
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return {7, 0, 0};
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if (Features.test(FeatureISAVersion7_0_1))
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return {7, 0, 1};
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if (Features.test(FeatureISAVersion7_0_2))
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return {7, 0, 2};
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// VI.
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if (Features.test(FeatureISAVersion8_0_0))
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return {8, 0, 0};
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if (Features.test(FeatureISAVersion8_0_1))
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return {8, 0, 1};
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if (Features.test(FeatureISAVersion8_0_2))
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return {8, 0, 2};
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if (Features.test(FeatureISAVersion8_0_3))
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return {8, 0, 3};
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if (Features.test(FeatureISAVersion8_0_4))
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return {8, 0, 4};
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if (Features.test(FeatureISAVersion8_1_0))
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return {8, 1, 0};
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if (!Features.test(FeatureGCN) || Features.test(FeatureSouthernIslands))
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return {0, 0, 0};
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return {7, 0, 0};
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}
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unsigned getWavefrontSize(const FeatureBitset &Features) {
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if (Features.test(FeatureWavefrontSize16))
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return 16;
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if (Features.test(FeatureWavefrontSize32))
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return 32;
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return 64;
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}
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unsigned getLocalMemorySize(const FeatureBitset &Features) {
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if (Features.test(FeatureLocalMemorySize32768))
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return 32768;
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if (Features.test(FeatureLocalMemorySize65536))
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return 65536;
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return 0;
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}
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unsigned getEUsPerCU(const FeatureBitset &Features) {
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return 4;
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}
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unsigned getMaxWorkGroupsPerCU(const FeatureBitset &Features,
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unsigned FlatWorkGroupSize) {
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if (!Features.test(FeatureGCN))
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return 8;
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unsigned N = getWavesPerWorkGroup(Features, FlatWorkGroupSize);
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if (N == 1)
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return 40;
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N = 40 / N;
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return std::min(N, 16u);
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}
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unsigned getMaxWavesPerCU(const FeatureBitset &Features) {
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return getMaxWavesPerEU(Features) * getEUsPerCU(Features);
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}
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unsigned getMaxWavesPerCU(const FeatureBitset &Features,
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unsigned FlatWorkGroupSize) {
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return getWavesPerWorkGroup(Features, FlatWorkGroupSize);
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}
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unsigned getMinWavesPerEU(const FeatureBitset &Features) {
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return 1;
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}
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unsigned getMaxWavesPerEU(const FeatureBitset &Features) {
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if (!Features.test(FeatureGCN))
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return 8;
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// FIXME: Need to take scratch memory into account.
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return 10;
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}
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unsigned getMaxWavesPerEU(const FeatureBitset &Features,
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unsigned FlatWorkGroupSize) {
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return alignTo(getMaxWavesPerCU(Features, FlatWorkGroupSize),
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getEUsPerCU(Features)) / getEUsPerCU(Features);
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}
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unsigned getMinFlatWorkGroupSize(const FeatureBitset &Features) {
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return 1;
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}
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unsigned getMaxFlatWorkGroupSize(const FeatureBitset &Features) {
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return 2048;
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}
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unsigned getWavesPerWorkGroup(const FeatureBitset &Features,
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unsigned FlatWorkGroupSize) {
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return alignTo(FlatWorkGroupSize, getWavefrontSize(Features)) /
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getWavefrontSize(Features);
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}
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unsigned getSGPRAllocGranule(const FeatureBitset &Features) {
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IsaVersion Version = getIsaVersion(Features);
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if (Version.Major >= 8)
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return 16;
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return 8;
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}
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unsigned getSGPREncodingGranule(const FeatureBitset &Features) {
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return 8;
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}
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unsigned getTotalNumSGPRs(const FeatureBitset &Features) {
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IsaVersion Version = getIsaVersion(Features);
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if (Version.Major >= 8)
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return 800;
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return 512;
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}
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unsigned getAddressableNumSGPRs(const FeatureBitset &Features) {
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if (Features.test(FeatureSGPRInitBug))
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return FIXED_NUM_SGPRS_FOR_INIT_BUG;
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IsaVersion Version = getIsaVersion(Features);
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if (Version.Major >= 8)
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return 102;
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return 104;
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}
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unsigned getMinNumSGPRs(const FeatureBitset &Features, unsigned WavesPerEU) {
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assert(WavesPerEU != 0);
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if (WavesPerEU >= getMaxWavesPerEU(Features))
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return 0;
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unsigned MinNumSGPRs =
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alignDown(getTotalNumSGPRs(Features) / (WavesPerEU + 1),
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getSGPRAllocGranule(Features)) + 1;
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return std::min(MinNumSGPRs, getAddressableNumSGPRs(Features));
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}
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unsigned getMaxNumSGPRs(const FeatureBitset &Features, unsigned WavesPerEU,
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bool Addressable) {
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assert(WavesPerEU != 0);
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IsaVersion Version = getIsaVersion(Features);
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unsigned MaxNumSGPRs = alignDown(getTotalNumSGPRs(Features) / WavesPerEU,
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getSGPRAllocGranule(Features));
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unsigned AddressableNumSGPRs = getAddressableNumSGPRs(Features);
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if (Version.Major >= 8 && !Addressable)
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AddressableNumSGPRs = 112;
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return std::min(MaxNumSGPRs, AddressableNumSGPRs);
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}
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unsigned getVGPRAllocGranule(const FeatureBitset &Features) {
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return 4;
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}
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unsigned getVGPREncodingGranule(const FeatureBitset &Features) {
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return getVGPRAllocGranule(Features);
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}
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unsigned getTotalNumVGPRs(const FeatureBitset &Features) {
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return 256;
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}
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unsigned getAddressableNumVGPRs(const FeatureBitset &Features) {
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return getTotalNumVGPRs(Features);
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}
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unsigned getMinNumVGPRs(const FeatureBitset &Features, unsigned WavesPerEU) {
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assert(WavesPerEU != 0);
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if (WavesPerEU >= getMaxWavesPerEU(Features))
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return 0;
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unsigned MinNumVGPRs =
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alignDown(getTotalNumVGPRs(Features) / (WavesPerEU + 1),
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getVGPRAllocGranule(Features)) + 1;
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return std::min(MinNumVGPRs, getAddressableNumVGPRs(Features));
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}
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unsigned getMaxNumVGPRs(const FeatureBitset &Features, unsigned WavesPerEU) {
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assert(WavesPerEU != 0);
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unsigned MaxNumVGPRs = alignDown(getTotalNumVGPRs(Features) / WavesPerEU,
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getVGPRAllocGranule(Features));
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unsigned AddressableNumVGPRs = getAddressableNumVGPRs(Features);
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return std::min(MaxNumVGPRs, AddressableNumVGPRs);
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}
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} // end namespace IsaInfo
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void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header,
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const FeatureBitset &Features) {
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IsaInfo::IsaVersion ISA = IsaInfo::getIsaVersion(Features);
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memset(&Header, 0, sizeof(Header));
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Header.amd_kernel_code_version_major = 1;
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Header.amd_kernel_code_version_minor = 0;
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Header.amd_machine_kind = 1; // AMD_MACHINE_KIND_AMDGPU
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Header.amd_machine_version_major = ISA.Major;
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Header.amd_machine_version_minor = ISA.Minor;
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Header.amd_machine_version_stepping = ISA.Stepping;
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Header.kernel_code_entry_byte_offset = sizeof(Header);
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// wavefront_size is specified as a power of 2: 2^6 = 64 threads.
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Header.wavefront_size = 6;
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// If the code object does not support indirect functions, then the value must
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// be 0xffffffff.
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Header.call_convention = -1;
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// These alignment values are specified in powers of two, so alignment =
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// 2^n. The minimum alignment is 2^4 = 16.
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Header.kernarg_segment_alignment = 4;
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Header.group_segment_alignment = 4;
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Header.private_segment_alignment = 4;
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}
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MCSection *getHSATextSection(MCContext &Ctx) {
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return Ctx.getELFSection(".hsatext", ELF::SHT_PROGBITS,
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ELF::SHF_ALLOC | ELF::SHF_WRITE |
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ELF::SHF_EXECINSTR |
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ELF::SHF_AMDGPU_HSA_AGENT |
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ELF::SHF_AMDGPU_HSA_CODE);
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}
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MCSection *getHSADataGlobalAgentSection(MCContext &Ctx) {
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return Ctx.getELFSection(".hsadata_global_agent", ELF::SHT_PROGBITS,
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ELF::SHF_ALLOC | ELF::SHF_WRITE |
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ELF::SHF_AMDGPU_HSA_GLOBAL |
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ELF::SHF_AMDGPU_HSA_AGENT);
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}
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MCSection *getHSADataGlobalProgramSection(MCContext &Ctx) {
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return Ctx.getELFSection(".hsadata_global_program", ELF::SHT_PROGBITS,
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ELF::SHF_ALLOC | ELF::SHF_WRITE |
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ELF::SHF_AMDGPU_HSA_GLOBAL);
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}
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MCSection *getHSARodataReadonlyAgentSection(MCContext &Ctx) {
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return Ctx.getELFSection(".hsarodata_readonly_agent", ELF::SHT_PROGBITS,
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ELF::SHF_ALLOC | ELF::SHF_AMDGPU_HSA_READONLY |
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ELF::SHF_AMDGPU_HSA_AGENT);
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}
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bool isGroupSegment(const GlobalValue *GV) {
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return GV->getType()->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS;
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}
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bool isGlobalSegment(const GlobalValue *GV) {
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return GV->getType()->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS;
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}
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bool isReadOnlySegment(const GlobalValue *GV) {
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return GV->getType()->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS;
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}
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bool shouldEmitConstantsToTextSection(const Triple &TT) {
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return TT.getOS() != Triple::AMDHSA;
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}
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int getIntegerAttribute(const Function &F, StringRef Name, int Default) {
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Attribute A = F.getFnAttribute(Name);
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int Result = Default;
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if (A.isStringAttribute()) {
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StringRef Str = A.getValueAsString();
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if (Str.getAsInteger(0, Result)) {
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LLVMContext &Ctx = F.getContext();
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Ctx.emitError("can't parse integer attribute " + Name);
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}
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}
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return Result;
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}
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std::pair<int, int> getIntegerPairAttribute(const Function &F,
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StringRef Name,
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std::pair<int, int> Default,
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bool OnlyFirstRequired) {
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Attribute A = F.getFnAttribute(Name);
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if (!A.isStringAttribute())
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return Default;
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LLVMContext &Ctx = F.getContext();
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std::pair<int, int> Ints = Default;
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std::pair<StringRef, StringRef> Strs = A.getValueAsString().split(',');
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if (Strs.first.trim().getAsInteger(0, Ints.first)) {
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Ctx.emitError("can't parse first integer attribute " + Name);
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return Default;
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}
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if (Strs.second.trim().getAsInteger(0, Ints.second)) {
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if (!OnlyFirstRequired || !Strs.second.trim().empty()) {
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Ctx.emitError("can't parse second integer attribute " + Name);
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return Default;
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}
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}
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return Ints;
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}
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unsigned getVmcntBitMask(const IsaInfo::IsaVersion &Version) {
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return (1 << getVmcntBitWidth()) - 1;
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}
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unsigned getExpcntBitMask(const IsaInfo::IsaVersion &Version) {
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return (1 << getExpcntBitWidth()) - 1;
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}
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unsigned getLgkmcntBitMask(const IsaInfo::IsaVersion &Version) {
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return (1 << getLgkmcntBitWidth()) - 1;
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}
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unsigned getWaitcntBitMask(const IsaInfo::IsaVersion &Version) {
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unsigned Vmcnt = getBitMask(getVmcntBitShift(), getVmcntBitWidth());
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unsigned Expcnt = getBitMask(getExpcntBitShift(), getExpcntBitWidth());
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unsigned Lgkmcnt = getBitMask(getLgkmcntBitShift(), getLgkmcntBitWidth());
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return Vmcnt | Expcnt | Lgkmcnt;
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}
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unsigned decodeVmcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt) {
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return unpackBits(Waitcnt, getVmcntBitShift(), getVmcntBitWidth());
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}
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unsigned decodeExpcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt) {
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return unpackBits(Waitcnt, getExpcntBitShift(), getExpcntBitWidth());
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}
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unsigned decodeLgkmcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt) {
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return unpackBits(Waitcnt, getLgkmcntBitShift(), getLgkmcntBitWidth());
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}
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void decodeWaitcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt,
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unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt) {
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Vmcnt = decodeVmcnt(Version, Waitcnt);
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Expcnt = decodeExpcnt(Version, Waitcnt);
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Lgkmcnt = decodeLgkmcnt(Version, Waitcnt);
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}
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unsigned encodeVmcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt,
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unsigned Vmcnt) {
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return packBits(Vmcnt, Waitcnt, getVmcntBitShift(), getVmcntBitWidth());
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}
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unsigned encodeExpcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt,
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unsigned Expcnt) {
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return packBits(Expcnt, Waitcnt, getExpcntBitShift(), getExpcntBitWidth());
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}
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unsigned encodeLgkmcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt,
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unsigned Lgkmcnt) {
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return packBits(Lgkmcnt, Waitcnt, getLgkmcntBitShift(), getLgkmcntBitWidth());
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}
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unsigned encodeWaitcnt(const IsaInfo::IsaVersion &Version,
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unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt) {
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unsigned Waitcnt = getWaitcntBitMask(Version);
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Waitcnt = encodeVmcnt(Version, Waitcnt, Vmcnt);
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Waitcnt = encodeExpcnt(Version, Waitcnt, Expcnt);
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Waitcnt = encodeLgkmcnt(Version, Waitcnt, Lgkmcnt);
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return Waitcnt;
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}
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unsigned getInitialPSInputAddr(const Function &F) {
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return getIntegerAttribute(F, "InitialPSInputAddr", 0);
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}
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bool isShader(CallingConv::ID cc) {
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switch(cc) {
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case CallingConv::AMDGPU_VS:
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case CallingConv::AMDGPU_GS:
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case CallingConv::AMDGPU_PS:
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case CallingConv::AMDGPU_CS:
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return true;
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default:
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return false;
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}
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}
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bool isCompute(CallingConv::ID cc) {
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return !isShader(cc) || cc == CallingConv::AMDGPU_CS;
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}
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bool isSI(const MCSubtargetInfo &STI) {
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return STI.getFeatureBits()[AMDGPU::FeatureSouthernIslands];
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}
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bool isCI(const MCSubtargetInfo &STI) {
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return STI.getFeatureBits()[AMDGPU::FeatureSeaIslands];
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}
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|
bool isVI(const MCSubtargetInfo &STI) {
|
|
return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands];
|
|
}
|
|
|
|
unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI) {
|
|
|
|
switch(Reg) {
|
|
default: break;
|
|
case AMDGPU::FLAT_SCR:
|
|
assert(!isSI(STI));
|
|
return isCI(STI) ? AMDGPU::FLAT_SCR_ci : AMDGPU::FLAT_SCR_vi;
|
|
|
|
case AMDGPU::FLAT_SCR_LO:
|
|
assert(!isSI(STI));
|
|
return isCI(STI) ? AMDGPU::FLAT_SCR_LO_ci : AMDGPU::FLAT_SCR_LO_vi;
|
|
|
|
case AMDGPU::FLAT_SCR_HI:
|
|
assert(!isSI(STI));
|
|
return isCI(STI) ? AMDGPU::FLAT_SCR_HI_ci : AMDGPU::FLAT_SCR_HI_vi;
|
|
}
|
|
return Reg;
|
|
}
|
|
|
|
bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo) {
|
|
assert(OpNo < Desc.NumOperands);
|
|
unsigned OpType = Desc.OpInfo[OpNo].OperandType;
|
|
return OpType >= AMDGPU::OPERAND_SRC_FIRST &&
|
|
OpType <= AMDGPU::OPERAND_SRC_LAST;
|
|
}
|
|
|
|
bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo) {
|
|
assert(OpNo < Desc.NumOperands);
|
|
unsigned OpType = Desc.OpInfo[OpNo].OperandType;
|
|
switch (OpType) {
|
|
case AMDGPU::OPERAND_REG_IMM_FP32:
|
|
case AMDGPU::OPERAND_REG_IMM_FP64:
|
|
case AMDGPU::OPERAND_REG_IMM_FP16:
|
|
case AMDGPU::OPERAND_REG_INLINE_C_FP32:
|
|
case AMDGPU::OPERAND_REG_INLINE_C_FP64:
|
|
case AMDGPU::OPERAND_REG_INLINE_C_FP16:
|
|
return true;
|
|
default:
|
|
return false;
|
|
}
|
|
}
|
|
|
|
bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo) {
|
|
assert(OpNo < Desc.NumOperands);
|
|
unsigned OpType = Desc.OpInfo[OpNo].OperandType;
|
|
return OpType >= AMDGPU::OPERAND_REG_INLINE_C_FIRST &&
|
|
OpType <= AMDGPU::OPERAND_REG_INLINE_C_LAST;
|
|
}
|
|
|
|
// Avoid using MCRegisterClass::getSize, since that function will go away
|
|
// (move from MC* level to Target* level). Return size in bits.
|
|
unsigned getRegBitWidth(unsigned RCID) {
|
|
switch (RCID) {
|
|
case AMDGPU::SGPR_32RegClassID:
|
|
case AMDGPU::VGPR_32RegClassID:
|
|
case AMDGPU::VS_32RegClassID:
|
|
case AMDGPU::SReg_32RegClassID:
|
|
case AMDGPU::SReg_32_XM0RegClassID:
|
|
return 32;
|
|
case AMDGPU::SGPR_64RegClassID:
|
|
case AMDGPU::VS_64RegClassID:
|
|
case AMDGPU::SReg_64RegClassID:
|
|
case AMDGPU::VReg_64RegClassID:
|
|
return 64;
|
|
case AMDGPU::VReg_96RegClassID:
|
|
return 96;
|
|
case AMDGPU::SGPR_128RegClassID:
|
|
case AMDGPU::SReg_128RegClassID:
|
|
case AMDGPU::VReg_128RegClassID:
|
|
return 128;
|
|
case AMDGPU::SReg_256RegClassID:
|
|
case AMDGPU::VReg_256RegClassID:
|
|
return 256;
|
|
case AMDGPU::SReg_512RegClassID:
|
|
case AMDGPU::VReg_512RegClassID:
|
|
return 512;
|
|
default:
|
|
llvm_unreachable("Unexpected register class");
|
|
}
|
|
}
|
|
|
|
unsigned getRegBitWidth(const MCRegisterClass &RC) {
|
|
return getRegBitWidth(RC.getID());
|
|
}
|
|
|
|
unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc,
|
|
unsigned OpNo) {
|
|
assert(OpNo < Desc.NumOperands);
|
|
unsigned RCID = Desc.OpInfo[OpNo].RegClass;
|
|
return getRegBitWidth(MRI->getRegClass(RCID)) / 8;
|
|
}
|
|
|
|
bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi) {
|
|
if (Literal >= -16 && Literal <= 64)
|
|
return true;
|
|
|
|
uint64_t Val = static_cast<uint64_t>(Literal);
|
|
return (Val == DoubleToBits(0.0)) ||
|
|
(Val == DoubleToBits(1.0)) ||
|
|
(Val == DoubleToBits(-1.0)) ||
|
|
(Val == DoubleToBits(0.5)) ||
|
|
(Val == DoubleToBits(-0.5)) ||
|
|
(Val == DoubleToBits(2.0)) ||
|
|
(Val == DoubleToBits(-2.0)) ||
|
|
(Val == DoubleToBits(4.0)) ||
|
|
(Val == DoubleToBits(-4.0)) ||
|
|
(Val == 0x3fc45f306dc9c882 && HasInv2Pi);
|
|
}
|
|
|
|
bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi) {
|
|
if (Literal >= -16 && Literal <= 64)
|
|
return true;
|
|
|
|
// The actual type of the operand does not seem to matter as long
|
|
// as the bits match one of the inline immediate values. For example:
|
|
//
|
|
// -nan has the hexadecimal encoding of 0xfffffffe which is -2 in decimal,
|
|
// so it is a legal inline immediate.
|
|
//
|
|
// 1065353216 has the hexadecimal encoding 0x3f800000 which is 1.0f in
|
|
// floating-point, so it is a legal inline immediate.
|
|
|
|
uint32_t Val = static_cast<uint32_t>(Literal);
|
|
return (Val == FloatToBits(0.0f)) ||
|
|
(Val == FloatToBits(1.0f)) ||
|
|
(Val == FloatToBits(-1.0f)) ||
|
|
(Val == FloatToBits(0.5f)) ||
|
|
(Val == FloatToBits(-0.5f)) ||
|
|
(Val == FloatToBits(2.0f)) ||
|
|
(Val == FloatToBits(-2.0f)) ||
|
|
(Val == FloatToBits(4.0f)) ||
|
|
(Val == FloatToBits(-4.0f)) ||
|
|
(Val == 0x3e22f983 && HasInv2Pi);
|
|
}
|
|
|
|
bool isInlinableLiteral16(int16_t Literal, bool HasInv2Pi) {
|
|
if (!HasInv2Pi)
|
|
return false;
|
|
|
|
if (Literal >= -16 && Literal <= 64)
|
|
return true;
|
|
|
|
uint16_t Val = static_cast<uint16_t>(Literal);
|
|
return Val == 0x3C00 || // 1.0
|
|
Val == 0xBC00 || // -1.0
|
|
Val == 0x3800 || // 0.5
|
|
Val == 0xB800 || // -0.5
|
|
Val == 0x4000 || // 2.0
|
|
Val == 0xC000 || // -2.0
|
|
Val == 0x4400 || // 4.0
|
|
Val == 0xC400 || // -4.0
|
|
Val == 0x3118; // 1/2pi
|
|
}
|
|
|
|
bool isUniformMMO(const MachineMemOperand *MMO) {
|
|
const Value *Ptr = MMO->getValue();
|
|
// UndefValue means this is a load of a kernel input. These are uniform.
|
|
// Sometimes LDS instructions have constant pointers.
|
|
// If Ptr is null, then that means this mem operand contains a
|
|
// PseudoSourceValue like GOT.
|
|
if (!Ptr || isa<UndefValue>(Ptr) || isa<Argument>(Ptr) ||
|
|
isa<Constant>(Ptr) || isa<GlobalValue>(Ptr))
|
|
return true;
|
|
|
|
const Instruction *I = dyn_cast<Instruction>(Ptr);
|
|
return I && I->getMetadata("amdgpu.uniform");
|
|
}
|
|
|
|
int64_t getSMRDEncodedOffset(const MCSubtargetInfo &ST, int64_t ByteOffset) {
|
|
if (isSI(ST) || isCI(ST))
|
|
return ByteOffset >> 2;
|
|
|
|
return ByteOffset;
|
|
}
|
|
|
|
bool isLegalSMRDImmOffset(const MCSubtargetInfo &ST, int64_t ByteOffset) {
|
|
int64_t EncodedOffset = getSMRDEncodedOffset(ST, ByteOffset);
|
|
return isSI(ST) || isCI(ST) ? isUInt<8>(EncodedOffset) :
|
|
isUInt<20>(EncodedOffset);
|
|
}
|
|
|
|
} // end namespace AMDGPU
|
|
} // end namespace llvm
|