Momchil Velikov 173b711e83 [ARM][MVE] MVE-I should not be disabled by -mfpu=none ... Architecturally, it's allowed to have MVE-I without an FPU, thus -mfpu=none should not disable MVE-I, or moves to/from FP-registers. This patch removes `+/-fpregs` from features unconditionally added to target feature list, depending on FPU and moves the logic to Clang driver, where the negative form (`-fpregs`) is conditionally added to the target features list for the cases of `-mfloat-abi=soft`, or `-mfpu=none` without either `+mve` or `+mve.fp`. Only the negative form is added by the driver, the positive one is derived from other features in the backend. Differential Revision: https://reviews.llvm.org/D71843		2020-01-09 14:03:25 +00:00
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arm-ieee-vectorize.ll	Migrate function attribute "no-frame-pointer-elim" to "frame-pointer"="all" as cleanups after D56351	2019-12-24 15:57:33 -08:00
arm-unroll.ll
gather-cost.ll
gcc-examples.ll
interleaved_cost.ll
lit.local.cfg
mul-cast-vect.ll
mve-interleaved-cost.ll	[ARM] Disable VLD4 under MVE	2019-12-08 10:37:29 +00:00
mve-maskedldst.ll	[ARM] Enable MVE masked loads and stores	2019-12-09 11:37:34 +00:00
mve-shiftcost.ll	[ARM][MVE] MVE-I should not be disabled by -mfpu=none	2020-01-09 14:03:25 +00:00
mve-vldn.ll	[ARM][MVE] MVE-I should not be disabled by -mfpu=none	2020-01-09 14:03:25 +00:00
prefer-tail-loop-folding.ll	[ARM] Enable MVE masked loads and stores	2019-12-09 11:37:34 +00:00
sphinx.ll
tail-folding-counting-down.ll	[LV] Still vectorise when tail-folding can't find a primary inducation variable	2020-01-09 09:14:00 +00:00
tail-loop-folding.ll	[ARM] Enable MVE masked loads and stores	2019-12-09 11:37:34 +00:00
vector_cast.ll
width-detect.ll