teak-llvm/llvm/test/MC/Disassembler/PowerPC
Victor Huang 5cee34013c [PowerPC][Future] Add prefixed instruction paddi to future CPU
Future CPU will include support for prefixed instructions.
These prefixed instructions are formed by a 4 byte prefix
immediately followed by a 4 byte instruction effectively
making an 8 byte instruction. The new instruction paddi
is a prefixed form of addi.

This patch adds paddi and all of the support required
for that instruction. The majority of the patch deals with
supporting the new prefixed instructions. The addition of
paddi is mainly to allow for testing.

Differential Revision: https://reviews.llvm.org/D72569
2020-01-24 07:27:25 -06:00
..
dcbt.txt
future-invalid.txt [PowerPC][Future] Add prefixed instruction paddi to future CPU 2020-01-24 07:27:25 -06:00
futureinsts.txt [PowerPC][Future] Add prefixed instruction paddi to future CPU 2020-01-24 07:27:25 -06:00
lit.local.cfg
ppc32-extpid-e500.txt
ppc64-encoding-4xx.txt
ppc64-encoding-6xx.txt
ppc64-encoding-bookII.txt
ppc64-encoding-bookIII.txt
ppc64-encoding-e500.txt
ppc64-encoding-ext.txt
ppc64-encoding-fp.txt
ppc64-encoding-p8htm.txt [PowerPC][HTM] Fix disassembling buffer overflow for tabortdc and others 2019-06-27 14:11:31 +00:00
ppc64-encoding-p8vector.txt
ppc64-encoding-p9vector.txt
ppc64-encoding-vmx.txt
ppc64-encoding.txt [PowerPC] Implementing overflow version for XO-Form instructions 2019-11-11 09:50:46 -06:00
ppc64-operands.txt
ppc64le-encoding.txt [PowerPC] Implementing overflow version for XO-Form instructions 2019-11-11 09:50:46 -06:00
qpx.txt
vsx.txt [PowerPC] Support extended mnemonics mffprwz etc. 2019-08-29 21:53:59 +00:00