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6af1be9664
We already use vmovq for v2i64/v2f64 vzmovl. But we were using a blendpd+xorpd for v4i64/v4f64/v8i64/v8f64 under opt speed. Or movsd+xorpd under optsize. I think the blend with 0 or movss/d is only needed for vXi32 where we don't have an instruction that can move 32 bits from one xmm to another while zeroing upper bits. movq is no worse than blendpd on any known CPUs. llvm-svn: 364079
121 lines
5.3 KiB
LLVM
121 lines
5.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=ALL --check-prefix=X32-SSE
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=ALL --check-prefix=X64-SSE
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; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=ALL --check-prefix=X32-AVX
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=ALL --check-prefix=X64-AVX
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define i64 @extract_any_extend_vector_inreg_v16i64(<16 x i64> %a0, i32 %a1) nounwind {
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; X32-SSE-LABEL: extract_any_extend_vector_inreg_v16i64:
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; X32-SSE: # %bb.0:
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; X32-SSE-NEXT: pushl %ebp
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; X32-SSE-NEXT: movl %esp, %ebp
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; X32-SSE-NEXT: andl $-128, %esp
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; X32-SSE-NEXT: subl $384, %esp # imm = 0x180
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; X32-SSE-NEXT: movl 88(%ebp), %ecx
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; X32-SSE-NEXT: movdqa 72(%ebp), %xmm0
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; X32-SSE-NEXT: psrldq {{.*#+}} xmm0 = xmm0[8,9,10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero
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; X32-SSE-NEXT: xorps %xmm1, %xmm1
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; X32-SSE-NEXT: movaps %xmm1, {{[0-9]+}}(%esp)
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; X32-SSE-NEXT: movaps %xmm1, {{[0-9]+}}(%esp)
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; X32-SSE-NEXT: movaps %xmm1, {{[0-9]+}}(%esp)
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; X32-SSE-NEXT: movaps %xmm1, {{[0-9]+}}(%esp)
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; X32-SSE-NEXT: movaps %xmm1, {{[0-9]+}}(%esp)
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; X32-SSE-NEXT: movaps %xmm1, {{[0-9]+}}(%esp)
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; X32-SSE-NEXT: movaps %xmm1, {{[0-9]+}}(%esp)
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; X32-SSE-NEXT: movdqa %xmm0, {{[0-9]+}}(%esp)
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; X32-SSE-NEXT: movaps %xmm1, {{[0-9]+}}(%esp)
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; X32-SSE-NEXT: movaps %xmm1, {{[0-9]+}}(%esp)
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; X32-SSE-NEXT: movaps %xmm1, {{[0-9]+}}(%esp)
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; X32-SSE-NEXT: movaps %xmm1, {{[0-9]+}}(%esp)
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; X32-SSE-NEXT: movaps %xmm1, {{[0-9]+}}(%esp)
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; X32-SSE-NEXT: movaps %xmm1, {{[0-9]+}}(%esp)
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; X32-SSE-NEXT: movaps %xmm1, (%esp)
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; X32-SSE-NEXT: movdqa %xmm0, {{[0-9]+}}(%esp)
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; X32-SSE-NEXT: leal (%ecx,%ecx), %eax
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; X32-SSE-NEXT: andl $31, %eax
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; X32-SSE-NEXT: movl 128(%esp,%eax,4), %eax
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; X32-SSE-NEXT: leal 1(%ecx,%ecx), %ecx
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; X32-SSE-NEXT: andl $31, %ecx
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; X32-SSE-NEXT: movl (%esp,%ecx,4), %edx
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; X32-SSE-NEXT: movl %ebp, %esp
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; X32-SSE-NEXT: popl %ebp
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; X32-SSE-NEXT: retl
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;
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; X64-SSE-LABEL: extract_any_extend_vector_inreg_v16i64:
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; X64-SSE: # %bb.0:
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; X64-SSE-NEXT: pushq %rbp
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; X64-SSE-NEXT: movq %rsp, %rbp
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; X64-SSE-NEXT: andq $-128, %rsp
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; X64-SSE-NEXT: subq $256, %rsp # imm = 0x100
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; X64-SSE-NEXT: # kill: def $edi killed $edi def $rdi
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; X64-SSE-NEXT: psrldq {{.*#+}} xmm7 = xmm7[8,9,10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero
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; X64-SSE-NEXT: xorps %xmm0, %xmm0
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; X64-SSE-NEXT: movaps %xmm0, {{[0-9]+}}(%rsp)
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; X64-SSE-NEXT: movaps %xmm0, {{[0-9]+}}(%rsp)
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; X64-SSE-NEXT: movaps %xmm0, {{[0-9]+}}(%rsp)
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; X64-SSE-NEXT: movaps %xmm0, {{[0-9]+}}(%rsp)
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; X64-SSE-NEXT: movaps %xmm0, {{[0-9]+}}(%rsp)
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; X64-SSE-NEXT: movaps %xmm0, {{[0-9]+}}(%rsp)
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; X64-SSE-NEXT: movaps %xmm0, (%rsp)
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; X64-SSE-NEXT: movdqa %xmm7, {{[0-9]+}}(%rsp)
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; X64-SSE-NEXT: andl $15, %edi
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; X64-SSE-NEXT: movq (%rsp,%rdi,8), %rax
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; X64-SSE-NEXT: movq %rbp, %rsp
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; X64-SSE-NEXT: popq %rbp
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; X64-SSE-NEXT: retq
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;
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; X32-AVX-LABEL: extract_any_extend_vector_inreg_v16i64:
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; X32-AVX: # %bb.0:
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; X32-AVX-NEXT: pushl %ebp
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; X32-AVX-NEXT: movl %esp, %ebp
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; X32-AVX-NEXT: andl $-128, %esp
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; X32-AVX-NEXT: subl $384, %esp # imm = 0x180
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; X32-AVX-NEXT: movl 40(%ebp), %ecx
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; X32-AVX-NEXT: vpbroadcastq 32(%ebp), %ymm0
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; X32-AVX-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero
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; X32-AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
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; X32-AVX-NEXT: vmovaps %ymm1, {{[0-9]+}}(%esp)
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; X32-AVX-NEXT: vmovaps %ymm1, {{[0-9]+}}(%esp)
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; X32-AVX-NEXT: vmovaps %ymm1, {{[0-9]+}}(%esp)
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; X32-AVX-NEXT: vmovdqa %ymm0, {{[0-9]+}}(%esp)
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; X32-AVX-NEXT: vmovaps %ymm1, {{[0-9]+}}(%esp)
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; X32-AVX-NEXT: vmovaps %ymm1, {{[0-9]+}}(%esp)
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; X32-AVX-NEXT: vmovaps %ymm1, (%esp)
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; X32-AVX-NEXT: vmovdqa %ymm0, {{[0-9]+}}(%esp)
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; X32-AVX-NEXT: leal (%ecx,%ecx), %eax
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; X32-AVX-NEXT: andl $31, %eax
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; X32-AVX-NEXT: movl 128(%esp,%eax,4), %eax
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; X32-AVX-NEXT: leal 1(%ecx,%ecx), %ecx
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; X32-AVX-NEXT: andl $31, %ecx
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; X32-AVX-NEXT: movl (%esp,%ecx,4), %edx
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; X32-AVX-NEXT: movl %ebp, %esp
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; X32-AVX-NEXT: popl %ebp
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; X32-AVX-NEXT: vzeroupper
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; X32-AVX-NEXT: retl
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;
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; X64-AVX-LABEL: extract_any_extend_vector_inreg_v16i64:
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; X64-AVX: # %bb.0:
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; X64-AVX-NEXT: pushq %rbp
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; X64-AVX-NEXT: movq %rsp, %rbp
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; X64-AVX-NEXT: andq $-128, %rsp
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; X64-AVX-NEXT: subq $256, %rsp # imm = 0x100
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; X64-AVX-NEXT: # kill: def $edi killed $edi def $rdi
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; X64-AVX-NEXT: vpermq {{.*#+}} ymm0 = ymm3[3,1,2,3]
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; X64-AVX-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero
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; X64-AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
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; X64-AVX-NEXT: vmovaps %ymm1, {{[0-9]+}}(%rsp)
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; X64-AVX-NEXT: vmovaps %ymm1, {{[0-9]+}}(%rsp)
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; X64-AVX-NEXT: vmovaps %ymm1, (%rsp)
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; X64-AVX-NEXT: vmovdqa %ymm0, {{[0-9]+}}(%rsp)
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; X64-AVX-NEXT: andl $15, %edi
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; X64-AVX-NEXT: movq (%rsp,%rdi,8), %rax
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; X64-AVX-NEXT: movq %rbp, %rsp
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; X64-AVX-NEXT: popq %rbp
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; X64-AVX-NEXT: vzeroupper
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; X64-AVX-NEXT: retq
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%1 = extractelement <16 x i64> %a0, i32 15
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%2 = insertelement <16 x i64> zeroinitializer, i64 %1, i32 4
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%3 = extractelement <16 x i64> %2, i32 %a1
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ret i64 %3
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}
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