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74168ded03
These were recently made simple types. This restores their behavior back to something like their EVT legalization. We might be able to fix the code in type legalization where the assert was failing, but I didn't investigate too much as I had already looked at the computeRegisterProperties code during the review for v3i16/v3f16. Most of the test changes restore the X86 codegen back to what it looked like before the recent change. The test case in vec_setcc.ll and is a reduced version of the reproducer from the fuzzer. Fixes https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=16490 llvm-svn: 369205
245 lines
7.9 KiB
LLVM
245 lines
7.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=SSE --check-prefix=SSE2
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE --check-prefix=SSE41
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX
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define <16 x i8> @v16i8_icmp_uge(<16 x i8> %a, <16 x i8> %b) nounwind readnone ssp uwtable {
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; SSE-LABEL: v16i8_icmp_uge:
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; SSE: # %bb.0:
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; SSE-NEXT: pmaxub %xmm0, %xmm1
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; SSE-NEXT: pcmpeqb %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: v16i8_icmp_uge:
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; AVX: # %bb.0:
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; AVX-NEXT: vpmaxub %xmm1, %xmm0, %xmm1
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; AVX-NEXT: vpcmpeqb %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = icmp uge <16 x i8> %a, %b
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%2 = sext <16 x i1> %1 to <16 x i8>
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ret <16 x i8> %2
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}
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define <16 x i8> @v16i8_icmp_ule(<16 x i8> %a, <16 x i8> %b) nounwind readnone ssp uwtable {
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; SSE-LABEL: v16i8_icmp_ule:
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; SSE: # %bb.0:
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; SSE-NEXT: pminub %xmm0, %xmm1
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; SSE-NEXT: pcmpeqb %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: v16i8_icmp_ule:
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; AVX: # %bb.0:
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; AVX-NEXT: vpminub %xmm1, %xmm0, %xmm1
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; AVX-NEXT: vpcmpeqb %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = icmp ule <16 x i8> %a, %b
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%2 = sext <16 x i1> %1 to <16 x i8>
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ret <16 x i8> %2
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}
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define <8 x i16> @v8i16_icmp_uge(<8 x i16> %a, <8 x i16> %b) nounwind readnone ssp uwtable {
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; SSE2-LABEL: v8i16_icmp_uge:
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; SSE2: # %bb.0:
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; SSE2-NEXT: psubusw %xmm0, %xmm1
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; SSE2-NEXT: pxor %xmm0, %xmm0
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; SSE2-NEXT: pcmpeqw %xmm1, %xmm0
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; SSE2-NEXT: retq
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;
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; SSE41-LABEL: v8i16_icmp_uge:
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; SSE41: # %bb.0:
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; SSE41-NEXT: pmaxuw %xmm0, %xmm1
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; SSE41-NEXT: pcmpeqw %xmm1, %xmm0
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; SSE41-NEXT: retq
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;
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; AVX-LABEL: v8i16_icmp_uge:
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; AVX: # %bb.0:
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; AVX-NEXT: vpmaxuw %xmm1, %xmm0, %xmm1
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; AVX-NEXT: vpcmpeqw %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = icmp uge <8 x i16> %a, %b
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%2 = sext <8 x i1> %1 to <8 x i16>
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ret <8 x i16> %2
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}
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define <8 x i16> @v8i16_icmp_ule(<8 x i16> %a, <8 x i16> %b) nounwind readnone ssp uwtable {
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; SSE2-LABEL: v8i16_icmp_ule:
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; SSE2: # %bb.0:
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; SSE2-NEXT: psubusw %xmm1, %xmm0
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; SSE2-NEXT: pxor %xmm1, %xmm1
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; SSE2-NEXT: pcmpeqw %xmm1, %xmm0
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; SSE2-NEXT: retq
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;
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; SSE41-LABEL: v8i16_icmp_ule:
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; SSE41: # %bb.0:
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; SSE41-NEXT: pminuw %xmm0, %xmm1
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; SSE41-NEXT: pcmpeqw %xmm1, %xmm0
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; SSE41-NEXT: retq
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;
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; AVX-LABEL: v8i16_icmp_ule:
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; AVX: # %bb.0:
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; AVX-NEXT: vpminuw %xmm1, %xmm0, %xmm1
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; AVX-NEXT: vpcmpeqw %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = icmp ule <8 x i16> %a, %b
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%2 = sext <8 x i1> %1 to <8 x i16>
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ret <8 x i16> %2
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}
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define <4 x i32> @v4i32_icmp_uge(<4 x i32> %a, <4 x i32> %b) nounwind readnone ssp uwtable {
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; SSE2-LABEL: v4i32_icmp_uge:
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; SSE2: # %bb.0:
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; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648]
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; SSE2-NEXT: pxor %xmm2, %xmm0
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; SSE2-NEXT: pxor %xmm1, %xmm2
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; SSE2-NEXT: pcmpgtd %xmm0, %xmm2
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; SSE2-NEXT: pcmpeqd %xmm0, %xmm0
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; SSE2-NEXT: pxor %xmm2, %xmm0
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; SSE2-NEXT: retq
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;
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; SSE41-LABEL: v4i32_icmp_uge:
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; SSE41: # %bb.0:
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; SSE41-NEXT: pmaxud %xmm0, %xmm1
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; SSE41-NEXT: pcmpeqd %xmm1, %xmm0
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; SSE41-NEXT: retq
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;
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; AVX-LABEL: v4i32_icmp_uge:
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; AVX: # %bb.0:
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; AVX-NEXT: vpmaxud %xmm1, %xmm0, %xmm1
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; AVX-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = icmp uge <4 x i32> %a, %b
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%2 = sext <4 x i1> %1 to <4 x i32>
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ret <4 x i32> %2
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}
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define <4 x i32> @v4i32_icmp_ule(<4 x i32> %a, <4 x i32> %b) nounwind readnone ssp uwtable {
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; SSE2-LABEL: v4i32_icmp_ule:
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; SSE2: # %bb.0:
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; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648]
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; SSE2-NEXT: pxor %xmm2, %xmm1
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; SSE2-NEXT: pxor %xmm2, %xmm0
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; SSE2-NEXT: pcmpgtd %xmm1, %xmm0
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; SSE2-NEXT: pcmpeqd %xmm1, %xmm1
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; SSE2-NEXT: pxor %xmm1, %xmm0
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; SSE2-NEXT: retq
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;
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; SSE41-LABEL: v4i32_icmp_ule:
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; SSE41: # %bb.0:
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; SSE41-NEXT: pminud %xmm0, %xmm1
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; SSE41-NEXT: pcmpeqd %xmm1, %xmm0
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; SSE41-NEXT: retq
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;
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; AVX-LABEL: v4i32_icmp_ule:
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; AVX: # %bb.0:
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; AVX-NEXT: vpminud %xmm1, %xmm0, %xmm1
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; AVX-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = icmp ule <4 x i32> %a, %b
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%2 = sext <4 x i1> %1 to <4 x i32>
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ret <4 x i32> %2
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}
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; At one point we were incorrectly constant-folding a setcc to 0x1 instead of
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; 0xff, leading to a constpool load. The instruction doesn't matter here, but it
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; should set all bits to 1.
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define <16 x i8> @test_setcc_constfold_vi8(<16 x i8> %l, <16 x i8> %r) {
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; SSE-LABEL: test_setcc_constfold_vi8:
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; SSE: # %bb.0:
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; SSE-NEXT: pcmpeqd %xmm0, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: test_setcc_constfold_vi8:
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; AVX: # %bb.0:
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; AVX-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
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; AVX-NEXT: retq
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%test1 = icmp eq <16 x i8> %l, %r
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%mask1 = sext <16 x i1> %test1 to <16 x i8>
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%test2 = icmp ne <16 x i8> %l, %r
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%mask2 = sext <16 x i1> %test2 to <16 x i8>
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%res = or <16 x i8> %mask1, %mask2
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ret <16 x i8> %res
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}
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; Make sure sensible results come from doing extension afterwards
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define <16 x i8> @test_setcc_constfold_vi1(<16 x i8> %l, <16 x i8> %r) {
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; SSE-LABEL: test_setcc_constfold_vi1:
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; SSE: # %bb.0:
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; SSE-NEXT: pcmpeqd %xmm0, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: test_setcc_constfold_vi1:
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; AVX: # %bb.0:
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; AVX-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
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; AVX-NEXT: retq
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%test1 = icmp eq <16 x i8> %l, %r
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%test2 = icmp ne <16 x i8> %l, %r
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%res = or <16 x i1> %test1, %test2
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%mask = sext <16 x i1> %res to <16 x i8>
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ret <16 x i8> %mask
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}
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; 64-bit case is also particularly important, as the constant "-1" is probably
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; just 32-bits wide.
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define <2 x i64> @test_setcc_constfold_vi64(<2 x i64> %l, <2 x i64> %r) {
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; SSE-LABEL: test_setcc_constfold_vi64:
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; SSE: # %bb.0:
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; SSE-NEXT: pcmpeqd %xmm0, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: test_setcc_constfold_vi64:
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; AVX: # %bb.0:
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; AVX-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
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; AVX-NEXT: retq
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%test1 = icmp eq <2 x i64> %l, %r
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%mask1 = sext <2 x i1> %test1 to <2 x i64>
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%test2 = icmp ne <2 x i64> %l, %r
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%mask2 = sext <2 x i1> %test2 to <2 x i64>
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%res = or <2 x i64> %mask1, %mask2
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ret <2 x i64> %res
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}
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; This asserted in type legalization for v3i1 setcc after v3i16 was made
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; a simple value type.
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define <3 x i1> @test_setcc_v3i1_v3i16(<3 x i16>* %a) nounwind {
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; SSE2-LABEL: test_setcc_v3i1_v3i16:
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; SSE2: # %bb.0:
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; SSE2-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
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; SSE2-NEXT: pxor %xmm1, %xmm1
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; SSE2-NEXT: pcmpeqw %xmm0, %xmm1
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; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
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; SSE2-NEXT: movdqa %xmm1, -{{[0-9]+}}(%rsp)
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; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al
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; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %dl
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; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %cl
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; SSE2-NEXT: retq
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;
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; SSE41-LABEL: test_setcc_v3i1_v3i16:
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; SSE41: # %bb.0:
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; SSE41-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
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; SSE41-NEXT: pxor %xmm1, %xmm1
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; SSE41-NEXT: pcmpeqw %xmm0, %xmm1
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; SSE41-NEXT: pextrb $0, %xmm1, %eax
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; SSE41-NEXT: pextrb $2, %xmm1, %edx
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; SSE41-NEXT: pextrb $4, %xmm1, %ecx
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; SSE41-NEXT: # kill: def $al killed $al killed $eax
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; SSE41-NEXT: # kill: def $dl killed $dl killed $edx
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; SSE41-NEXT: # kill: def $cl killed $cl killed $ecx
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; SSE41-NEXT: retq
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;
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; AVX-LABEL: test_setcc_v3i1_v3i16:
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; AVX: # %bb.0:
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; AVX-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero
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; AVX-NEXT: vpxor %xmm1, %xmm1, %xmm1
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; AVX-NEXT: vpcmpeqw %xmm1, %xmm0, %xmm0
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; AVX-NEXT: vpextrb $0, %xmm0, %eax
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; AVX-NEXT: vpextrb $2, %xmm0, %edx
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; AVX-NEXT: vpextrb $4, %xmm0, %ecx
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; AVX-NEXT: # kill: def $al killed $al killed $eax
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; AVX-NEXT: # kill: def $dl killed $dl killed $edx
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; AVX-NEXT: # kill: def $cl killed $cl killed $ecx
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; AVX-NEXT: retq
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%b = load <3 x i16>, <3 x i16>* %a
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%cmp = icmp eq <3 x i16> %b, <i16 0, i16 0, i16 0>
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ret <3 x i1> %cmp
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}
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