mirror of
https://github.com/Gericom/teak-llvm.git
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f97b29be88
Summary: The DAGCombiner is rewriting (canonicalizing) an ISD::ADD with no common bits set in the operands as an ISD::OR node. This could sometimes result in "missing out" on some combines that normally are performed for ADD. To be more specific this could happen if we already have rewritten an ADD into OR, and later (after legalizations or combines) we expose patterns that could have been optimized if we had seen the OR as an ADD (e.g. reassociations based on ADD). To make the DAG combiner less sensitive to if ADD or OR is used for these "no common bits set" ADD/OR operations we now apply most of the ADD combines also to an OR operation, when value tracking indicates that the operands have no common bits set. Reviewers: spatel, RKSimon, craig.topper, kparzysz Reviewed By: spatel Subscribers: arsenm, rampitec, lebedev.ri, jvesely, nhaehnle, hiraditya, javed.absar, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59758 llvm-svn: 358965
278 lines
8.0 KiB
LLVM
278 lines
8.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=x86_64-unknown-unknown -force-split-store < %s | FileCheck %s
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define void @int32_float_pair(i32 %tmp1, float %tmp2, i64* %ref.tmp) {
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; CHECK-LABEL: int32_float_pair:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl %edi, (%rsi)
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; CHECK-NEXT: movss %xmm0, 4(%rsi)
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; CHECK-NEXT: retq
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%t0 = bitcast float %tmp2 to i32
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%t1 = zext i32 %t0 to i64
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%t2 = shl nuw i64 %t1, 32
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%t3 = zext i32 %tmp1 to i64
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%t4 = or i64 %t2, %t3
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store i64 %t4, i64* %ref.tmp, align 8
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ret void
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}
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define void @float_int32_pair(float %tmp1, i32 %tmp2, i64* %ref.tmp) {
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; CHECK-LABEL: float_int32_pair:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movss %xmm0, (%rsi)
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; CHECK-NEXT: movl %edi, 4(%rsi)
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; CHECK-NEXT: retq
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%t0 = bitcast float %tmp1 to i32
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%t1 = zext i32 %tmp2 to i64
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%t2 = shl nuw i64 %t1, 32
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%t3 = zext i32 %t0 to i64
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%t4 = or i64 %t2, %t3
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store i64 %t4, i64* %ref.tmp, align 8
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ret void
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}
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define void @int16_float_pair(i16 signext %tmp1, float %tmp2, i64* %ref.tmp) {
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; CHECK-LABEL: int16_float_pair:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movzwl %di, %eax
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; CHECK-NEXT: movl %eax, (%rsi)
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; CHECK-NEXT: movss %xmm0, 4(%rsi)
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; CHECK-NEXT: retq
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%t0 = bitcast float %tmp2 to i32
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%t1 = zext i32 %t0 to i64
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%t2 = shl nuw i64 %t1, 32
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%t3 = zext i16 %tmp1 to i64
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%t4 = or i64 %t2, %t3
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store i64 %t4, i64* %ref.tmp, align 8
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ret void
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}
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define void @int8_float_pair(i8 signext %tmp1, float %tmp2, i64* %ref.tmp) {
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; CHECK-LABEL: int8_float_pair:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movzbl %dil, %eax
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; CHECK-NEXT: movl %eax, (%rsi)
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; CHECK-NEXT: movss %xmm0, 4(%rsi)
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; CHECK-NEXT: retq
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%t0 = bitcast float %tmp2 to i32
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%t1 = zext i32 %t0 to i64
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%t2 = shl nuw i64 %t1, 32
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%t3 = zext i8 %tmp1 to i64
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%t4 = or i64 %t2, %t3
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store i64 %t4, i64* %ref.tmp, align 8
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ret void
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}
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define void @int32_int32_pair(i32 %tmp1, i32 %tmp2, i64* %ref.tmp) {
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; CHECK-LABEL: int32_int32_pair:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl %edi, (%rdx)
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; CHECK-NEXT: movl %esi, 4(%rdx)
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; CHECK-NEXT: retq
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%t1 = zext i32 %tmp2 to i64
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%t2 = shl nuw i64 %t1, 32
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%t3 = zext i32 %tmp1 to i64
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%t4 = or i64 %t2, %t3
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store i64 %t4, i64* %ref.tmp, align 8
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ret void
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}
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define void @int16_int16_pair(i16 signext %tmp1, i16 signext %tmp2, i32* %ref.tmp) {
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; CHECK-LABEL: int16_int16_pair:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movw %di, (%rdx)
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; CHECK-NEXT: movw %si, 2(%rdx)
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; CHECK-NEXT: retq
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%t1 = zext i16 %tmp2 to i32
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%t2 = shl nuw i32 %t1, 16
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%t3 = zext i16 %tmp1 to i32
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%t4 = or i32 %t2, %t3
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store i32 %t4, i32* %ref.tmp, align 4
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ret void
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}
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define void @int8_int8_pair(i8 signext %tmp1, i8 signext %tmp2, i16* %ref.tmp) {
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; CHECK-LABEL: int8_int8_pair:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movb %dil, (%rdx)
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; CHECK-NEXT: movb %sil, 1(%rdx)
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; CHECK-NEXT: retq
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%t1 = zext i8 %tmp2 to i16
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%t2 = shl nuw i16 %t1, 8
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%t3 = zext i8 %tmp1 to i16
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%t4 = or i16 %t2, %t3
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store i16 %t4, i16* %ref.tmp, align 2
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ret void
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}
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define void @int31_int31_pair(i31 %tmp1, i31 %tmp2, i64* %ref.tmp) {
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; CHECK-LABEL: int31_int31_pair:
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; CHECK: # %bb.0:
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; CHECK-NEXT: andl $2147483647, %edi # imm = 0x7FFFFFFF
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; CHECK-NEXT: movl %edi, (%rdx)
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; CHECK-NEXT: andl $2147483647, %esi # imm = 0x7FFFFFFF
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; CHECK-NEXT: movl %esi, 4(%rdx)
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; CHECK-NEXT: retq
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%t1 = zext i31 %tmp2 to i64
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%t2 = shl nuw i64 %t1, 32
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%t3 = zext i31 %tmp1 to i64
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%t4 = or i64 %t2, %t3
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store i64 %t4, i64* %ref.tmp, align 8
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ret void
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}
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define void @int31_int17_pair(i31 %tmp1, i17 %tmp2, i64* %ref.tmp) {
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; CHECK-LABEL: int31_int17_pair:
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; CHECK: # %bb.0:
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; CHECK-NEXT: andl $2147483647, %edi # imm = 0x7FFFFFFF
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; CHECK-NEXT: movl %edi, (%rdx)
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; CHECK-NEXT: andl $131071, %esi # imm = 0x1FFFF
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; CHECK-NEXT: movl %esi, 4(%rdx)
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; CHECK-NEXT: retq
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%t1 = zext i17 %tmp2 to i64
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%t2 = shl nuw i64 %t1, 32
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%t3 = zext i31 %tmp1 to i64
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%t4 = or i64 %t2, %t3
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store i64 %t4, i64* %ref.tmp, align 8
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ret void
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}
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define void @int7_int3_pair(i7 signext %tmp1, i3 signext %tmp2, i16* %ref.tmp) {
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; CHECK-LABEL: int7_int3_pair:
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; CHECK: # %bb.0:
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; CHECK-NEXT: andb $127, %dil
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; CHECK-NEXT: movb %dil, (%rdx)
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; CHECK-NEXT: andb $7, %sil
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; CHECK-NEXT: movb %sil, 1(%rdx)
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; CHECK-NEXT: retq
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%t1 = zext i3 %tmp2 to i16
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%t2 = shl nuw i16 %t1, 8
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%t3 = zext i7 %tmp1 to i16
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%t4 = or i16 %t2, %t3
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store i16 %t4, i16* %ref.tmp, align 2
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ret void
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}
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define void @int24_int24_pair(i24 signext %tmp1, i24 signext %tmp2, i48* %ref.tmp) {
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; CHECK-LABEL: int24_int24_pair:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movw %di, (%rdx)
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; CHECK-NEXT: shrl $16, %edi
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; CHECK-NEXT: movb %dil, 2(%rdx)
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; CHECK-NEXT: movw %si, 4(%rdx)
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; CHECK-NEXT: shrl $16, %esi
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; CHECK-NEXT: movb %sil, 6(%rdx)
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; CHECK-NEXT: retq
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%t1 = zext i24 %tmp2 to i48
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%t2 = shl nuw i48 %t1, 24
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%t3 = zext i24 %tmp1 to i48
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%t4 = or i48 %t2, %t3
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store i48 %t4, i48* %ref.tmp, align 2
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ret void
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}
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; getTypeSizeInBits(i12) != getTypeStoreSizeInBits(i12), so store split doesn't kick in.
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define void @int12_int12_pair(i12 signext %tmp1, i12 signext %tmp2, i24* %ref.tmp) {
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; CHECK-LABEL: int12_int12_pair:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl %esi, %eax
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; CHECK-NEXT: shll $12, %eax
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; CHECK-NEXT: andl $4095, %edi # imm = 0xFFF
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; CHECK-NEXT: orl %eax, %edi
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; CHECK-NEXT: shrl $4, %esi
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; CHECK-NEXT: movb %sil, 2(%rdx)
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; CHECK-NEXT: movw %di, (%rdx)
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; CHECK-NEXT: retq
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%t1 = zext i12 %tmp2 to i24
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%t2 = shl nuw i24 %t1, 12
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%t3 = zext i12 %tmp1 to i24
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%t4 = or i24 %t2, %t3
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store i24 %t4, i24* %ref.tmp, align 2
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ret void
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}
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; getTypeSizeInBits(i14) != getTypeStoreSizeInBits(i14), so store split doesn't kick in.
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define void @int7_int7_pair(i7 signext %tmp1, i7 signext %tmp2, i14* %ref.tmp) {
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; CHECK-LABEL: int7_int7_pair:
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; CHECK: # %bb.0:
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; CHECK-NEXT: shll $7, %esi
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; CHECK-NEXT: andl $127, %edi
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; CHECK-NEXT: orl %esi, %edi
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; CHECK-NEXT: andl $16383, %edi # imm = 0x3FFF
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; CHECK-NEXT: movw %di, (%rdx)
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; CHECK-NEXT: retq
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%t1 = zext i7 %tmp2 to i14
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%t2 = shl nuw i14 %t1, 7
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%t3 = zext i7 %tmp1 to i14
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%t4 = or i14 %t2, %t3
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store i14 %t4, i14* %ref.tmp, align 2
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ret void
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}
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; getTypeSizeInBits(i2) != getTypeStoreSizeInBits(i2), so store split doesn't kick in.
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define void @int1_int1_pair(i1 signext %tmp1, i1 signext %tmp2, i2* %ref.tmp) {
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; CHECK-LABEL: int1_int1_pair:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addb %sil, %sil
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; CHECK-NEXT: subb %dil, %sil
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; CHECK-NEXT: andb $3, %sil
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; CHECK-NEXT: movb %sil, (%rdx)
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; CHECK-NEXT: retq
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%t1 = zext i1 %tmp2 to i2
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%t2 = shl nuw i2 %t1, 1
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%t3 = zext i1 %tmp1 to i2
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%t4 = or i2 %t2, %t3
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store i2 %t4, i2* %ref.tmp, align 1
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ret void
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}
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define void @mbb_int32_float_pair(i32 %tmp1, float %tmp2, i64* %ref.tmp) {
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; CHECK-LABEL: mbb_int32_float_pair:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: movl %edi, (%rsi)
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; CHECK-NEXT: movss %xmm0, 4(%rsi)
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; CHECK-NEXT: retq
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entry:
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%t0 = bitcast float %tmp2 to i32
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br label %next
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next:
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%t1 = zext i32 %t0 to i64
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%t2 = shl nuw i64 %t1, 32
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%t3 = zext i32 %tmp1 to i64
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%t4 = or i64 %t2, %t3
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store i64 %t4, i64* %ref.tmp, align 8
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ret void
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}
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define void @mbb_int32_float_multi_stores(i32 %tmp1, float %tmp2, i64* %ref.tmp, i64* %ref.tmp1, i1 %cmp) {
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; CHECK-LABEL: mbb_int32_float_multi_stores:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: movl %edi, (%rsi)
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; CHECK-NEXT: movss %xmm0, 4(%rsi)
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; CHECK-NEXT: testb $1, %cl
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; CHECK-NEXT: je .LBB15_2
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; CHECK-NEXT: # %bb.1: # %bb2
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; CHECK-NEXT: movl %edi, (%rdx)
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; CHECK-NEXT: movss %xmm0, 4(%rdx)
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; CHECK-NEXT: .LBB15_2: # %exitbb
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; CHECK-NEXT: retq
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entry:
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%t0 = bitcast float %tmp2 to i32
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br label %bb1
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bb1:
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%t1 = zext i32 %t0 to i64
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%t2 = shl nuw i64 %t1, 32
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%t3 = zext i32 %tmp1 to i64
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%t4 = or i64 %t2, %t3
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store i64 %t4, i64* %ref.tmp, align 8
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br i1 %cmp, label %bb2, label %exitbb
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bb2:
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store i64 %t4, i64* %ref.tmp1, align 8
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br label %exitbb
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exitbb:
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ret void
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}
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