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https://github.com/Gericom/teak-llvm.git
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828b685ebe
Trace through multiple COPYs when looking for a physreg source. Add hinting for vregs that will be copied into physregs (we only hinted for vregs getting copied to a physreg previously). Give hinted a register a bonus when deciding which value to spill. This is part of my rewrite regallocfast series. In fact this one doesn't even have an effect unless you also flip the allocation to happen from back to front of a basic block. Nonetheless it helps to split this up to ease review of D52010 Patch by Matthias Braun llvm-svn: 360887
94 lines
3.7 KiB
LLVM
94 lines
3.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -O0 -relocation-model=pic -frame-pointer=all < %s | FileCheck %s
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
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target triple = "x86_64-apple-darwin10"
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; This file contains functions that may crash llc -O0
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; The DIV8 instruction produces results in AH and AL, but we don't want to use
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; AH in 64-bit mode. The hack used must not generate copyFromReg nodes for
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; aliased registers (AX and AL) - RegAllocFast does not like that.
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; PR7312
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define i32 @div8() nounwind {
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; CHECK-LABEL: div8:
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; CHECK: ## %bb.0: ## %entry
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; CHECK-NEXT: pushq %rbp
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; CHECK-NEXT: movq %rsp, %rbp
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: ## kill: def $al killed $al killed $eax
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; CHECK-NEXT: ## implicit-def: $rcx
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; CHECK-NEXT: ## kill: def $cl killed $cl killed $rcx
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; CHECK-NEXT: movb %al, {{[-0-9]+}}(%r{{[sb]}}p) ## 1-byte Spill
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; CHECK-NEXT: movzbw %al, %ax
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; CHECK-NEXT: divb %cl
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; CHECK-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %dl ## 1-byte Reload
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; CHECK-NEXT: movb %al, {{[-0-9]+}}(%r{{[sb]}}p) ## 1-byte Spill
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; CHECK-NEXT: movzbw %dl, %ax
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; CHECK-NEXT: divb %cl
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; CHECK-NEXT: shrw $8, %ax
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; CHECK-NEXT: ## kill: def $al killed $al killed $ax
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; CHECK-NEXT: cmpb %cl, %al
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; CHECK-NEXT: jae LBB0_2
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; CHECK-NEXT: ## %bb.1: ## %"39"
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; CHECK-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al ## 1-byte Reload
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; CHECK-NEXT: movzbl %al, %ecx
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; CHECK-NEXT: ## implicit-def: $edx
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; CHECK-NEXT: imull %edx, %ecx
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; CHECK-NEXT: addl %edx, %ecx
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; CHECK-NEXT: cmpl %edx, %ecx
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; CHECK-NEXT: je LBB0_3
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; CHECK-NEXT: LBB0_2: ## %"40"
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; CHECK-NEXT: ud2
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; CHECK-NEXT: LBB0_3: ## %"41"
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; CHECK-NEXT: ud2
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entry:
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%0 = trunc i64 undef to i8 ; <i8> [#uses=3]
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%1 = udiv i8 0, %0 ; <i8> [#uses=1]
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%2 = urem i8 0, %0 ; <i8> [#uses=1]
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%3 = icmp uge i8 %2, %0 ; <i1> [#uses=1]
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br i1 %3, label %"40", label %"39"
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"39": ; preds = %"36"
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%4 = zext i8 %1 to i32 ; <i32> [#uses=1]
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%5 = mul nsw i32 %4, undef ; <i32> [#uses=1]
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%6 = add nsw i32 %5, undef ; <i32> [#uses=1]
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%7 = icmp ne i32 %6, undef ; <i1> [#uses=1]
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br i1 %7, label %"40", label %"41"
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"40": ; preds = %"39", %"36"
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unreachable
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"41": ; preds = %"39"
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unreachable
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}
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; When using fast isel, sdiv is lowered into a sequence of CQO + DIV64.
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; CQO defines implicitly AX and DIV64 uses it implicitly too.
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; When an instruction gets between those two, RegAllocFast was reusing
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; AX for the vreg defined in between and the compiler crashed.
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;
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; An instruction gets between CQO and DIV64 because the load is folded
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; into the division but it requires a sign extension.
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; PR21700
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define i64 @addressModeWith32bitIndex(i32 %V) {
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; CHECK-LABEL: addressModeWith32bitIndex:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: pushq %rbp
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: .cfi_offset %rbp, -16
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; CHECK-NEXT: movq %rsp, %rbp
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; CHECK-NEXT: .cfi_def_cfa_register %rbp
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: movl %eax, %ecx
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; CHECK-NEXT: movq %rcx, %rax
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; CHECK-NEXT: cqto
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; CHECK-NEXT: movslq %edi, %rsi
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; CHECK-NEXT: idivq (%rcx,%rsi,8)
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; CHECK-NEXT: popq %rbp
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; CHECK-NEXT: retq
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%gep = getelementptr i64, i64* null, i32 %V
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%load = load i64, i64* %gep
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%sdiv = sdiv i64 0, %load
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ret i64 %sdiv
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}
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