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https://github.com/Gericom/teak-llvm.git
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5e51f75542
We were previously not necessarily favouring postinc for the MVE loads and stores, leading to extra code prior to the loop to set up the preinc. MVE in general can benefit from postinc (as we don't have unrolled loops), and certain instructions like the VLD2's only post-inc versions are available. Differential Revision: https://reviews.llvm.org/D70790
195 lines
6.8 KiB
LLVM
195 lines
6.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp %s -o - | FileCheck %s
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define arm_aapcs_vfpcc <4 x i32> @vmlau32(<4 x i32> %A, <4 x i32> %B, i32 %X) nounwind {
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; CHECK-LABEL: vmlau32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmla.u32 q0, q1, r0
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; CHECK-NEXT: bx lr
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entry:
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%0 = insertelement <4 x i32> undef, i32 %X, i32 0
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%1 = shufflevector <4 x i32> %0, <4 x i32> undef, <4 x i32> zeroinitializer
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%2 = mul nsw <4 x i32> %B, %1
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%3 = add nsw <4 x i32> %A, %2
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ret <4 x i32> %3
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}
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define arm_aapcs_vfpcc <4 x i32> @vmlau32b(<4 x i32> %A, <4 x i32> %B, i32 %X) nounwind {
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; CHECK-LABEL: vmlau32b:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmla.u32 q0, q1, r0
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; CHECK-NEXT: bx lr
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entry:
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%0 = insertelement <4 x i32> undef, i32 %X, i32 0
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%1 = shufflevector <4 x i32> %0, <4 x i32> undef, <4 x i32> zeroinitializer
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%2 = mul nsw <4 x i32> %1, %B
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%3 = add nsw <4 x i32> %2, %A
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ret <4 x i32> %3
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}
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define arm_aapcs_vfpcc <8 x i16> @vmlau16(<8 x i16> %A, <8 x i16> %B, i16 %X) nounwind {
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; CHECK-LABEL: vmlau16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmla.u16 q0, q1, r0
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; CHECK-NEXT: bx lr
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entry:
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%0 = insertelement <8 x i16> undef, i16 %X, i32 0
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%1 = shufflevector <8 x i16> %0, <8 x i16> undef, <8 x i32> zeroinitializer
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%2 = mul nsw <8 x i16> %B, %1
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%3 = add nsw <8 x i16> %A, %2
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ret <8 x i16> %3
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}
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define arm_aapcs_vfpcc <8 x i16> @vmlau16b(<8 x i16> %A, <8 x i16> %B, i16 %X) nounwind {
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; CHECK-LABEL: vmlau16b:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmla.u16 q0, q1, r0
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; CHECK-NEXT: bx lr
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entry:
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%0 = insertelement <8 x i16> undef, i16 %X, i32 0
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%1 = shufflevector <8 x i16> %0, <8 x i16> undef, <8 x i32> zeroinitializer
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%2 = mul nsw <8 x i16> %1, %B
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%3 = add nsw <8 x i16> %2, %A
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ret <8 x i16> %3
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}
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define arm_aapcs_vfpcc <16 x i8> @vmlau8(<16 x i8> %A, <16 x i8> %B, i8 %X) nounwind {
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; CHECK-LABEL: vmlau8:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmla.u8 q0, q1, r0
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; CHECK-NEXT: bx lr
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entry:
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%0 = insertelement <16 x i8> undef, i8 %X, i32 0
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%1 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> zeroinitializer
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%2 = mul nsw <16 x i8> %B, %1
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%3 = add nsw <16 x i8> %A, %2
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ret <16 x i8> %3
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}
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define arm_aapcs_vfpcc <16 x i8> @vmlau8b(<16 x i8> %A, <16 x i8> %B, i8 %X) nounwind {
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; CHECK-LABEL: vmlau8b:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmla.u8 q0, q1, r0
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; CHECK-NEXT: bx lr
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entry:
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%0 = insertelement <16 x i8> undef, i8 %X, i32 0
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%1 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> zeroinitializer
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%2 = mul nsw <16 x i8> %1, %B
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%3 = add nsw <16 x i8> %2, %A
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ret <16 x i8> %3
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}
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define void @vmla32_in_loop(i32* %s1, i32 %x, i32* %d, i32 %n) {
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; CHECK-LABEL: vmla32_in_loop:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .LBB6_1: @ %vector.body
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; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: vldrw.u32 q0, [r0], #16
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; CHECK-NEXT: vldrw.u32 q1, [r2]
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; CHECK-NEXT: subs r3, #4
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; CHECK-NEXT: vmla.u32 q1, q0, r1
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; CHECK-NEXT: vstrb.8 q1, [r2], #16
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; CHECK-NEXT: bne .LBB6_1
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; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup
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; CHECK-NEXT: bx lr
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entry:
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%broadcast.splatinsert8 = insertelement <4 x i32> undef, i32 %x, i32 0
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%broadcast.splat9 = shufflevector <4 x i32> %broadcast.splatinsert8, <4 x i32> undef, <4 x i32> zeroinitializer
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br label %vector.body
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vector.body:
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%index = phi i32 [ 0, %entry ], [ %index.next, %vector.body ]
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%0 = getelementptr inbounds i32, i32* %s1, i32 %index
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%1 = bitcast i32* %0 to <4 x i32>*
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%wide.load = load <4 x i32>, <4 x i32>* %1, align 4
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%2 = mul nsw <4 x i32> %wide.load, %broadcast.splat9
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%3 = getelementptr inbounds i32, i32* %d, i32 %index
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%4 = bitcast i32* %3 to <4 x i32>*
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%wide.load10 = load <4 x i32>, <4 x i32>* %4, align 4
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%5 = add nsw <4 x i32> %wide.load10, %2
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%6 = bitcast i32* %3 to <4 x i32>*
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store <4 x i32> %5, <4 x i32>* %6, align 4
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%index.next = add i32 %index, 4
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%7 = icmp eq i32 %index.next, %n
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br i1 %7, label %for.cond.cleanup, label %vector.body
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for.cond.cleanup:
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ret void
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}
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define void @vmla16_in_loop(i16* %s1, i16 %x, i16* %d, i32 %n) {
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; CHECK-LABEL: vmla16_in_loop:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .LBB7_1: @ %vector.body
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; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: vldrh.u16 q0, [r0], #16
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; CHECK-NEXT: vldrh.u16 q1, [r2]
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; CHECK-NEXT: subs r3, #8
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; CHECK-NEXT: vmla.u16 q1, q0, r1
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; CHECK-NEXT: vstrb.8 q1, [r2], #16
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; CHECK-NEXT: bne .LBB7_1
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; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup
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; CHECK-NEXT: bx lr
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entry:
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%broadcast.splatinsert11 = insertelement <8 x i16> undef, i16 %x, i32 0
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%broadcast.splat12 = shufflevector <8 x i16> %broadcast.splatinsert11, <8 x i16> undef, <8 x i32> zeroinitializer
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br label %vector.body
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vector.body:
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%index = phi i32 [ 0, %entry ], [ %index.next, %vector.body ]
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%0 = getelementptr inbounds i16, i16* %s1, i32 %index
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%1 = bitcast i16* %0 to <8 x i16>*
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%wide.load = load <8 x i16>, <8 x i16>* %1, align 2
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%2 = mul <8 x i16> %wide.load, %broadcast.splat12
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%3 = getelementptr inbounds i16, i16* %d, i32 %index
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%4 = bitcast i16* %3 to <8 x i16>*
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%wide.load13 = load <8 x i16>, <8 x i16>* %4, align 2
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%5 = add <8 x i16> %2, %wide.load13
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%6 = bitcast i16* %3 to <8 x i16>*
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store <8 x i16> %5, <8 x i16>* %6, align 2
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%index.next = add i32 %index, 8
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%7 = icmp eq i32 %index.next, %n
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br i1 %7, label %for.cond.cleanup, label %vector.body
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for.cond.cleanup:
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ret void
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}
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define void @vmla8_in_loop(i8* %s1, i8 %x, i8* %d, i32 %n) {
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; CHECK-LABEL: vmla8_in_loop:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .LBB8_1: @ %vector.body
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; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: vldrh.u16 q0, [r0], #16
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; CHECK-NEXT: vldrh.u16 q1, [r2]
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; CHECK-NEXT: subs r3, #16
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; CHECK-NEXT: vmla.u8 q1, q0, r1
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; CHECK-NEXT: vstrb.8 q1, [r2], #16
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; CHECK-NEXT: bne .LBB8_1
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; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup
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; CHECK-NEXT: bx lr
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entry:
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%broadcast.splatinsert11 = insertelement <16 x i8> undef, i8 %x, i32 0
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%broadcast.splat12 = shufflevector <16 x i8> %broadcast.splatinsert11, <16 x i8> undef, <16 x i32> zeroinitializer
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br label %vector.body
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vector.body:
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%index = phi i32 [ 0, %entry ], [ %index.next, %vector.body ]
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%0 = getelementptr inbounds i8, i8* %s1, i32 %index
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%1 = bitcast i8* %0 to <16 x i8>*
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%wide.load = load <16 x i8>, <16 x i8>* %1, align 2
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%2 = mul <16 x i8> %wide.load, %broadcast.splat12
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%3 = getelementptr inbounds i8, i8* %d, i32 %index
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%4 = bitcast i8* %3 to <16 x i8>*
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%wide.load13 = load <16 x i8>, <16 x i8>* %4, align 2
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%5 = add <16 x i8> %2, %wide.load13
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%6 = bitcast i8* %3 to <16 x i8>*
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store <16 x i8> %5, <16 x i8>* %6, align 2
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%index.next = add i32 %index, 16
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%7 = icmp eq i32 %index.next, %n
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br i1 %7, label %for.cond.cleanup, label %vector.body
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for.cond.cleanup:
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ret void
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}
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