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https://github.com/Gericom/teak-llvm.git
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fb8c9a339a
This adds extra scalar handling to isFMAFasterThanFMulAndFAdd, allowing the target independent code to handle more folds in more situations (for example if the fast math flags are present, but the global AllowFPOpFusion option isnt). It also splits apart the HasSlowFPVMLx into HasSlowFPVFMx, to allow VFMA and VMLA to be controlled separately if needed. Differential Revision: https://reviews.llvm.org/D72139
232 lines
6.6 KiB
LLVM
232 lines
6.6 KiB
LLVM
; RUN: llc < %s -mtriple=thumbv7-none-eabi -mcpu=cortex-m3 | FileCheck %s -check-prefix=CHECK -check-prefix=SOFT -check-prefix=NONE
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; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-m4 | FileCheck %s -check-prefix=CHECK -check-prefix=SOFT -check-prefix=SP
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; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-m7 | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=DP -check-prefix=VFP -check-prefix=FP-ARMv8
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; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-m7 -mattr=-fp64 | FileCheck %s -check-prefix=CHECK -check-prefix=SOFT -check-prefix=SP
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; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-a7 | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=DP -check-prefix=NEON -check-prefix=VFP4
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; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-a57 | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=DP -check-prefix=NEON -check-prefix=FP-ARMv8
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declare double @llvm.sqrt.f64(double %Val)
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define double @sqrt_d(double %a) {
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; CHECK-LABEL: sqrt_d:
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; SOFT: {{(bl|b)}} sqrt
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; HARD: vsqrt.f64 d0, d0
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%1 = call double @llvm.sqrt.f64(double %a)
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ret double %1
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}
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declare double @llvm.powi.f64(double %Val, i32 %power)
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define double @powi_d(double %a, i32 %b) {
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; CHECK-LABEL: powi_d:
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; SOFT: {{(bl|b)}} __powidf2
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; HARD: b __powidf2
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%1 = call double @llvm.powi.f64(double %a, i32 %b)
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ret double %1
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}
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declare double @llvm.sin.f64(double %Val)
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define double @sin_d(double %a) {
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; CHECK-LABEL: sin_d:
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; SOFT: {{(bl|b)}} sin
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; HARD: b sin
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%1 = call double @llvm.sin.f64(double %a)
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ret double %1
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}
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declare double @llvm.cos.f64(double %Val)
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define double @cos_d(double %a) {
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; CHECK-LABEL: cos_d:
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; SOFT: {{(bl|b)}} cos
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; HARD: b cos
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%1 = call double @llvm.cos.f64(double %a)
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ret double %1
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}
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declare double @llvm.pow.f64(double %Val, double %power)
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define double @pow_d(double %a, double %b) {
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; CHECK-LABEL: pow_d:
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; SOFT: {{(bl|b)}} pow
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; HARD: b pow
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%1 = call double @llvm.pow.f64(double %a, double %b)
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ret double %1
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}
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declare double @llvm.exp.f64(double %Val)
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define double @exp_d(double %a) {
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; CHECK-LABEL: exp_d:
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; SOFT: {{(bl|b)}} exp
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; HARD: b exp
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%1 = call double @llvm.exp.f64(double %a)
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ret double %1
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}
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declare double @llvm.exp2.f64(double %Val)
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define double @exp2_d(double %a) {
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; CHECK-LABEL: exp2_d:
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; SOFT: {{(bl|b)}} exp2
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; HARD: b exp2
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%1 = call double @llvm.exp2.f64(double %a)
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ret double %1
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}
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declare double @llvm.log.f64(double %Val)
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define double @log_d(double %a) {
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; CHECK-LABEL: log_d:
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; SOFT: {{(bl|b)}} log
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; HARD: b log
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%1 = call double @llvm.log.f64(double %a)
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ret double %1
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}
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declare double @llvm.log10.f64(double %Val)
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define double @log10_d(double %a) {
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; CHECK-LABEL: log10_d:
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; SOFT: {{(bl|b)}} log10
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; HARD: b log10
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%1 = call double @llvm.log10.f64(double %a)
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ret double %1
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}
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declare double @llvm.log2.f64(double %Val)
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define double @log2_d(double %a) {
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; CHECK-LABEL: log2_d:
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; SOFT: {{(bl|b)}} log2
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; HARD: b log2
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%1 = call double @llvm.log2.f64(double %a)
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ret double %1
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}
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declare double @llvm.fma.f64(double %a, double %b, double %c)
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define double @fma_d(double %a, double %b, double %c) {
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; CHECK-LABEL: fma_d:
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; SOFT: {{(bl|b)}} fma
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; HARD: vfma.f64
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%1 = call double @llvm.fma.f64(double %a, double %b, double %c)
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ret double %1
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}
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; FIXME: the FPv4-SP version is less efficient than the no-FPU version
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declare double @llvm.fabs.f64(double %Val)
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define double @abs_d(double %a) {
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; CHECK-LABEL: abs_d:
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; NONE: bic r1, r1, #-2147483648
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; SP: vldr d1, .LCPI{{.*}}
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; SP: vmov r0, r1, d0
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; SP: vmov r2, r3, d1
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; SP: lsrs r2, r3, #31
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; SP: bfi r1, r2, #31, #1
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; SP: vmov d0, r0, r1
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; DP: vabs.f64 d0, d0
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%1 = call double @llvm.fabs.f64(double %a)
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ret double %1
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}
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declare double @llvm.copysign.f64(double %Mag, double %Sgn)
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define double @copysign_d(double %a, double %b) {
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; CHECK-LABEL: copysign_d:
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; SOFT: lsrs [[REG:r[0-9]+]], r3, #31
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; SOFT: bfi r1, [[REG]], #31, #1
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; VFP: lsrs [[REG:r[0-9]+]], r3, #31
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; VFP: bfi r1, [[REG]], #31, #1
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; NEON: vmov.i32 [[REG:d[0-9]+]], #0x80000000
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; NEON: vshl.i64 [[REG]], [[REG]], #32
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; NEON: vbsl [[REG]], d
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%1 = call double @llvm.copysign.f64(double %a, double %b)
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ret double %1
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}
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declare double @llvm.floor.f64(double %Val)
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define double @floor_d(double %a) {
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; CHECK-LABEL: floor_d:
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; SOFT: {{(bl|b)}} floor
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; VFP4: b floor
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; FP-ARMv8: vrintm.f64
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%1 = call double @llvm.floor.f64(double %a)
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ret double %1
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}
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declare double @llvm.ceil.f64(double %Val)
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define double @ceil_d(double %a) {
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; CHECK-LABEL: ceil_d:
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; SOFT: {{(bl|b)}} ceil
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; VFP4: b ceil
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; FP-ARMv8: vrintp.f64
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%1 = call double @llvm.ceil.f64(double %a)
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ret double %1
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}
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declare double @llvm.trunc.f64(double %Val)
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define double @trunc_d(double %a) {
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; CHECK-LABEL: trunc_d:
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; SOFT: {{(bl|b)}} trunc
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; FFP4: b trunc
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; FP-ARMv8: vrintz.f64
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%1 = call double @llvm.trunc.f64(double %a)
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ret double %1
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}
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declare double @llvm.rint.f64(double %Val)
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define double @rint_d(double %a) {
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; CHECK-LABEL: rint_d:
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; SOFT: {{(bl|b)}} rint
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; VFP4: b rint
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; FP-ARMv8: vrintx.f64
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%1 = call double @llvm.rint.f64(double %a)
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ret double %1
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}
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declare double @llvm.nearbyint.f64(double %Val)
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define double @nearbyint_d(double %a) {
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; CHECK-LABEL: nearbyint_d:
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; SOFT: {{(bl|b)}} nearbyint
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; VFP4: b nearbyint
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; FP-ARMv8: vrintr.f64
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%1 = call double @llvm.nearbyint.f64(double %a)
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ret double %1
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}
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declare double @llvm.round.f64(double %Val)
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define double @round_d(double %a) {
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; CHECK-LABEL: round_d:
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; SOFT: {{(bl|b)}} round
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; VFP4: b round
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; FP-ARMv8: vrinta.f64
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%1 = call double @llvm.round.f64(double %a)
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ret double %1
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}
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declare double @llvm.fmuladd.f64(double %a, double %b, double %c)
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define double @fmuladd_d(double %a, double %b, double %c) {
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; CHECK-LABEL: fmuladd_d:
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; SOFT: bl __aeabi_dmul
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; SOFT: bl __aeabi_dadd
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; VFP4: vmul.f64
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; VFP4: vadd.f64
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; FP-ARMv8: vfma.f64
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%1 = call double @llvm.fmuladd.f64(double %a, double %b, double %c)
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ret double %1
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}
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declare i16 @llvm.convert.to.fp16.f64(double %a)
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define i16 @d_to_h(double %a) {
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; CHECK-LABEL: d_to_h:
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; SOFT: bl __aeabi_d2h
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; VFP4: bl __aeabi_d2h
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; FP-ARMv8: vcvt{{[bt]}}.f16.f64
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%1 = call i16 @llvm.convert.to.fp16.f64(double %a)
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ret i16 %1
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}
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declare double @llvm.convert.from.fp16.f64(i16 %a)
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define double @h_to_d(i16 %a) {
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; CHECK-LABEL: h_to_d:
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; NONE: bl __aeabi_h2f
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; NONE: bl __aeabi_f2d
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; SP: vcvt{{[bt]}}.f32.f16
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; SP: bl __aeabi_f2d
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; VFPv4: vcvt{{[bt]}}.f32.f16
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; VFPv4: vcvt.f64.f32
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; FP-ARMv8: vcvt{{[bt]}}.f64.f16
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%1 = call double @llvm.convert.from.fp16.f64(i16 %a)
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ret double %1
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}
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