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https://github.com/Gericom/teak-llvm.git
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d91a9e27a9
This will remove suboptimal branching from the generated ll/sc loops. The extra simplification pass affects a lot of testcases, which have been modified to accommodate this change: either by modifying the test to become immune to the CFG simplification, or (less preferablt) by adding option -hexagon-initial-cfg-clenaup=0. llvm-svn: 338774
24 lines
861 B
LLVM
24 lines
861 B
LLVM
; RUN: llc -march=hexagon < %s | FileCheck %s
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; Check for successful compilation.
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; CHECK: sfcmp
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target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
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target triple = "hexagon"
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@g0 = global <8 x i32> zeroinitializer, align 8
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define void @fred(<8 x float>* %a0, <8 x float>* %a1) #0 {
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b0:
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%v0 = load <8 x float>, <8 x float>* %a1, align 8
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%v1 = fcmp olt <8 x float> %v0, zeroinitializer
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%v2 = load <8 x float>, <8 x float>* %a0, align 8
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%v3 = fcmp olt <8 x float> %v2, zeroinitializer
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%v4 = and <8 x i1> %v1, %v3
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%v5 = zext <8 x i1> %v4 to <8 x i32>
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store <8 x i32> %v5, <8 x i32>* @g0, align 8
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ret void
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}
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attributes #0 = { noinline norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvx-length64b,+hvxv60" }
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