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2ac1162917
The "dead" markings allow existing target-independent optimizations, like MachineSink, to trigger more frequently. The CPSR defs would have eventually been marked dead by LiveVariables, so this only affects optimizations before regalloc. The ARMBaseInstrInfo.cpp change is fixing a bug which is only visible with this change: the transform adds a use to an otherwise dead def of CPSR. This is covered by existing regression tests. thumb2-tbh.ll breaks for Thumb1 due to MachineLICM changing the generated code; I'll fix it in D53452. Differential Revision: https://reviews.llvm.org/D53453 llvm-svn: 345420
60 lines
1.5 KiB
LLVM
60 lines
1.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple thumbv7-eabi | FileCheck %s -check-prefix=T2
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; RUN: llc < %s -mtriple thumbv6m-eabi | FileCheck %s -check-prefix=T1
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; <rdar://problem/7569620>
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define i32 @compare_i_gt(i32 %a) {
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; T2-LABEL: compare_i_gt:
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; T2: @ %bb.0: @ %entry
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; T2-NEXT: movs r1, #24
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; T2-NEXT: cmn.w r0, #78
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; T2-NEXT: it gt
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; T2-NEXT: movgt r1, #42
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; T2-NEXT: mov r0, r1
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; T2-NEXT: bx lr
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;
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; T1-LABEL: compare_i_gt:
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; T1: @ %bb.0: @ %entry
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; T1-NEXT: movs r1, #77
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; T1-NEXT: mvns r1, r1
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; T1-NEXT: cmp r0, r1
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; T1-NEXT: bgt .LBB0_2
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; T1-NEXT: @ %bb.1: @ %entry
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; T1-NEXT: movs r0, #24
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; T1-NEXT: bx lr
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; T1-NEXT: .LBB0_2:
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; T1-NEXT: movs r0, #42
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; T1-NEXT: bx lr
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entry:
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%cmp = icmp sgt i32 %a, -78
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%ret = select i1 %cmp, i32 42, i32 24
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ret i32 %ret
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}
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define i32 @compare_r_eq(i32 %a, i32 %b) {
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; T2-LABEL: compare_r_eq:
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; T2: @ %bb.0: @ %entry
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; T2-NEXT: movs r2, #24
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; T2-NEXT: cmn r0, r1
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; T2-NEXT: it eq
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; T2-NEXT: moveq r2, #42
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; T2-NEXT: mov r0, r2
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; T2-NEXT: bx lr
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;
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; T1-LABEL: compare_r_eq:
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; T1: @ %bb.0: @ %entry
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; T1-NEXT: cmn r0, r1
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; T1-NEXT: beq .LBB1_2
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; T1-NEXT: @ %bb.1: @ %entry
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; T1-NEXT: movs r0, #24
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; T1-NEXT: bx lr
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; T1-NEXT: .LBB1_2:
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; T1-NEXT: movs r0, #42
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; T1-NEXT: bx lr
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entry:
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%sub = sub nsw i32 0, %b
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%cmp = icmp eq i32 %a, %sub
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%ret = select i1 %cmp, i32 42, i32 24
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ret i32 %ret
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}
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