mirror of
https://github.com/Gericom/teak-llvm.git
synced 2025-06-20 03:55:48 -04:00
b777e551f0
Summary: Mem op clustering adds a weak edge in the DAG between two loads or stores that should be clustered, but the direction of this edge is pretty arbitrary (it depends on the sort order of MemOpInfo, which represents the operands of a load or store). This often means that two loads or stores will get reordered even if they would naturally have been scheduled together anyway, which leads to test case churn and goes against the scheduler's "do no harm" philosophy. The fix makes sure that the direction of the edge always matches the original code order of the instructions. Reviewers: atrick, MatzeB, arsenm, rampitec, t.p.northover Subscribers: jvesely, wdng, nhaehnle, kristof.beyls, hiraditya, javed.absar, arphaman, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D72706
133 lines
5.2 KiB
LLVM
133 lines
5.2 KiB
LLVM
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx900 -mattr=-code-object-v3 -amdgpu-ir-lower-kernel-arguments=0 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=VI,GCN,HSA-VI,FUNC %s
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; Repeat of some problematic tests in kernel-args.ll, with the IR
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; argument lowering pass disabled. Struct padding needs to be
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; accounted for, as well as legalization of types changing offsets.
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; FUNC-LABEL: {{^}}i1_arg:
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; HSA-VI: kernarg_segment_byte_size = 12
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; HSA-VI: kernarg_segment_alignment = 4
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; GCN: s_load_dword s
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; GCN: s_and_b32
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define amdgpu_kernel void @i1_arg(i1 addrspace(1)* %out, i1 %x) nounwind {
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store i1 %x, i1 addrspace(1)* %out, align 1
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ret void
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}
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; FUNC-LABEL: {{^}}v3i8_arg:
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; HSA-VI: kernarg_segment_byte_size = 12
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; HSA-VI: kernarg_segment_alignment = 4
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; HSA-VI: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s[4:5], 0x0
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; HSA-VI: s_load_dword s{{[0-9]+}}, s[4:5], 0x8
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define amdgpu_kernel void @v3i8_arg(<3 x i8> addrspace(1)* nocapture %out, <3 x i8> %in) nounwind {
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entry:
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store <3 x i8> %in, <3 x i8> addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}i65_arg:
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; HSA-VI: kernarg_segment_byte_size = 24
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; HSA-VI: kernarg_segment_alignment = 4
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; HSA-VI: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s[4:5], 0x0
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; HSA-VI: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s[4:5], 0x8
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define amdgpu_kernel void @i65_arg(i65 addrspace(1)* nocapture %out, i65 %in) nounwind {
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entry:
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store i65 %in, i65 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}empty_struct_arg:
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; HSA-VI: kernarg_segment_byte_size = 0
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define amdgpu_kernel void @empty_struct_arg({} %in) nounwind {
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ret void
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}
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; The correct load offsets for these:
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; load 4 from 0,
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; load 8 from 8
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; load 4 from 24
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; load 8 from 32
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; With the SelectionDAG argument lowering, the alignments for the
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; struct members is not properly considered, making these wrong.
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; FIXME: Total argument size is computed wrong
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; FUNC-LABEL: {{^}}struct_argument_alignment:
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; HSA-VI: kernarg_segment_byte_size = 40
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; HSA-VI: s_load_dword s{{[0-9]+}}, s[4:5], 0x0
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; HSA-VI: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s[4:5], 0x8
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; HSA-VI: s_load_dword s{{[0-9]+}}, s[4:5], 0x18
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; HSA-VI: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s[4:5], 0x20
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define amdgpu_kernel void @struct_argument_alignment({i32, i64} %arg0, i8, {i32, i64} %arg1) {
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%val0 = extractvalue {i32, i64} %arg0, 0
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%val1 = extractvalue {i32, i64} %arg0, 1
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%val2 = extractvalue {i32, i64} %arg1, 0
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%val3 = extractvalue {i32, i64} %arg1, 1
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store volatile i32 %val0, i32 addrspace(1)* null
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store volatile i64 %val1, i64 addrspace(1)* null
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store volatile i32 %val2, i32 addrspace(1)* null
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store volatile i64 %val3, i64 addrspace(1)* null
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ret void
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}
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; No padding between i8 and next struct, but round up at end to 4 byte
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; multiple.
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; FUNC-LABEL: {{^}}packed_struct_argument_alignment:
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; HSA-VI: kernarg_segment_byte_size = 28
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; HSA-VI: global_load_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, off offset:17
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; HSA-VI: global_load_dword v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, off offset:13
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; HSA-VI: s_load_dword s{{[0-9]+}}, s[4:5], 0x0
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; HSA-VI: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s[4:5], 0x4
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define amdgpu_kernel void @packed_struct_argument_alignment(<{i32, i64}> %arg0, i8, <{i32, i64}> %arg1) {
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%val0 = extractvalue <{i32, i64}> %arg0, 0
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%val1 = extractvalue <{i32, i64}> %arg0, 1
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%val2 = extractvalue <{i32, i64}> %arg1, 0
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%val3 = extractvalue <{i32, i64}> %arg1, 1
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store volatile i32 %val0, i32 addrspace(1)* null
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store volatile i64 %val1, i64 addrspace(1)* null
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store volatile i32 %val2, i32 addrspace(1)* null
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store volatile i64 %val3, i64 addrspace(1)* null
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ret void
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}
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; GCN-LABEL: {{^}}struct_argument_alignment_after:
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; HSA-VI: kernarg_segment_byte_size = 64
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; HSA-VI: s_load_dword s{{[0-9]+}}, s[4:5], 0x0
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; HSA-VI: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s[4:5], 0x8
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; HSA-VI: s_load_dword s{{[0-9]+}}, s[4:5], 0x18
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; HSA-VI: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s[4:5], 0x20
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; HSA-VI: s_load_dwordx4 s{{\[[0-9]+:[0-9]+\]}}, s[4:5], 0x30
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define amdgpu_kernel void @struct_argument_alignment_after({i32, i64} %arg0, i8, {i32, i64} %arg2, i8, <4 x i32> %arg4) {
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%val0 = extractvalue {i32, i64} %arg0, 0
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%val1 = extractvalue {i32, i64} %arg0, 1
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%val2 = extractvalue {i32, i64} %arg2, 0
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%val3 = extractvalue {i32, i64} %arg2, 1
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store volatile i32 %val0, i32 addrspace(1)* null
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store volatile i64 %val1, i64 addrspace(1)* null
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store volatile i32 %val2, i32 addrspace(1)* null
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store volatile i64 %val3, i64 addrspace(1)* null
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store volatile <4 x i32> %arg4, <4 x i32> addrspace(1)* null
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ret void
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}
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; GCN-LABEL: {{^}}array_3xi32:
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; HSA-VI: s_load_dword s{{[0-9]+}}, s[4:5], 0x0
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; HSA-VI: s_load_dword s{{[0-9]+}}, s[4:5], 0x4
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; HSA-VI: s_load_dword s{{[0-9]+}}, s[4:5], 0x8
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; HSA-VI: s_load_dword s{{[0-9]+}}, s[4:5], 0xc
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define amdgpu_kernel void @array_3xi32(i16 %arg0, [3 x i32] %arg1) {
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store volatile i16 %arg0, i16 addrspace(1)* undef
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store volatile [3 x i32] %arg1, [3 x i32] addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}array_3xi16:
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; HSA-VI: s_load_dword s{{[0-9]+}}, s[4:5], 0x0
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; HSA-VI: s_load_dword s{{[0-9]+}}, s[4:5], 0x4
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define amdgpu_kernel void @array_3xi16(i8 %arg0, [3 x i16] %arg1) {
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store volatile i8 %arg0, i8 addrspace(1)* undef
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store volatile [3 x i16] %arg1, [3 x i16] addrspace(1)* undef
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ret void
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}
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