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7cd57dcd5b
We handle it this way for some other address spaces. Since r349196, SILoadStoreOptimizer has been trying to do this. This is after SIFoldOperands runs, which can change the addressing patterns. It's simpler to just split this earlier. llvm-svn: 375366
103 lines
5.3 KiB
LLVM
103 lines
5.3 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -amdgpu-enable-global-sgpr-addr < %s | FileCheck -check-prefix=GFX9 %s
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; Test for a conv2d like sequence of loads.
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; GFX9: global_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}} offset:16{{$}}
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; GFX9: global_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}{{$}}
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; GFX9: global_load_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}} offset:32{{$}}
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; GFX9: global_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}} offset:-16{{$}}
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; GFX9: global_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}} offset:-32{{$}}
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; GFX9: global_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}} offset:8{{$}}
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define hidden amdgpu_kernel void @simpleSaddrs(i64 addrspace(1)* %dst_image, i64 addrspace(1)* %src_image ) {
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entry:
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%id = call i32 @llvm.amdgcn.workitem.id.x()
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%idx = zext i32 %id to i64
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%gep = getelementptr i64, i64 addrspace(1)* %src_image, i64 %idx
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%ptr0 = getelementptr inbounds i64, i64 addrspace(1)* %gep, i64 1
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%load0 = load i64, i64 addrspace(1)* %ptr0
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%ptr1 = getelementptr inbounds i64, i64 addrspace(1)* %gep, i64 2
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%load1 = load i64, i64 addrspace(1)* %ptr1
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%ptr2 = getelementptr inbounds i64, i64 addrspace(1)* %gep, i64 3
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%load2 = load i64, i64 addrspace(1)* %ptr2
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%ptr3 = getelementptr inbounds i64, i64 addrspace(1)* %gep, i64 4
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%load3 = load i64, i64 addrspace(1)* %ptr3
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%ptr4 = getelementptr inbounds i64, i64 addrspace(1)* %gep, i64 -4
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%load4 = load i64, i64 addrspace(1)* %ptr4
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%ptr5 = getelementptr inbounds i64, i64 addrspace(1)* %gep, i64 -3
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%load5 = load i64, i64 addrspace(1)* %ptr5
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%ptr6 = getelementptr inbounds i64, i64 addrspace(1)* %gep, i64 -2
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%load6 = load i64, i64 addrspace(1)* %ptr6
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%ptr7 = getelementptr inbounds i64, i64 addrspace(1)* %gep, i64 -1
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%load7 = load i64, i64 addrspace(1)* %ptr7
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%ptr8 = getelementptr inbounds i64, i64 addrspace(1)* %gep, i64 0
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%load8 = load i64, i64 addrspace(1)* %ptr8
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%add0 = add i64 %load1, %load0
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%add1 = add i64 %load3, %load2
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%add2 = add i64 %load5, %load4
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%add3 = add i64 %load7, %load6
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%add4 = add i64 %add0, %load8
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%add5 = add i64 %add2, %add1
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%add6 = add i64 %add4, %add3
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%add7 = add i64 %add6, %add5
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%gep9 = getelementptr i64, i64 addrspace(1)* %dst_image, i64 %idx
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%ptr9 = getelementptr inbounds i64, i64 addrspace(1)* %gep9, i64 1
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store volatile i64 %add7, i64 addrspace(1)* %ptr9
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; Test various offset boundaries.
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; GFX9: global_load_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+}}:{{[0-9]+}}] offset:4088{{$}}
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; GFX9: global_load_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, off offset:4088{{$}}
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; GFX9: global_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+}}:{{[0-9]+}}] offset:2040{{$}}
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%gep11 = getelementptr inbounds i64, i64 addrspace(1)* %gep, i64 511
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%load11 = load i64, i64 addrspace(1)* %gep11
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%gep12 = getelementptr inbounds i64, i64 addrspace(1)* %gep, i64 1023
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%load12 = load i64, i64 addrspace(1)* %gep12
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%gep13 = getelementptr inbounds i64, i64 addrspace(1)* %gep, i64 255
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%load13 = load i64, i64 addrspace(1)* %gep13
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%add11 = add i64 %load11, %load12
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%add12 = add i64 %add11, %load13
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store volatile i64 %add12, i64 addrspace(1)* undef
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; GFX9: global_load_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, off{{$}}
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; GFX9: global_load_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, off{{$}}
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; GFX9: global_load_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+}}:{{[0-9]+}}] offset:-4096{{$}}
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%gep21 = getelementptr inbounds i64, i64 addrspace(1)* %gep, i64 -1024
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%load21 = load i64, i64 addrspace(1)* %gep21
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%gep22 = getelementptr inbounds i64, i64 addrspace(1)* %gep, i64 -2048
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%load22 = load i64, i64 addrspace(1)* %gep22
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%gep23 = getelementptr inbounds i64, i64 addrspace(1)* %gep, i64 -512
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%load23 = load i64, i64 addrspace(1)* %gep23
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%add21 = add i64 %load22, %load21
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%add22 = add i64 %add21, %load23
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store volatile i64 %add22, i64 addrspace(1)* undef
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; GFX9: global_load_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+}}:{{[0-9]+}}] offset:2040{{$}}
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%gep31 = getelementptr inbounds i64, i64 addrspace(1)* %gep, i64 257
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%load31 = load i64, i64 addrspace(1)* %gep31
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%gep32 = getelementptr inbounds i64, i64 addrspace(1)* %gep, i64 256
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%load32 = load i64, i64 addrspace(1)* %gep32
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%gep33 = getelementptr inbounds i64, i64 addrspace(1)* %gep, i64 255
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%load33 = load i64, i64 addrspace(1)* %gep33
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%add34 = add i64 %load32, %load31
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%add35 = add i64 %add34, %load33
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store volatile i64 %add35, i64 addrspace(1)* undef
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ret void
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}
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; GFX9: global_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, off{{$}}
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; GFX9: global_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, off offset:16{{$}}
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; GFX9-NEXT: s_waitcnt
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; NGFX9-NOT: global_load_dword
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define amdgpu_cs void @_amdgpu_cs_main(i64 inreg %arg) {
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bb:
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%tmp1 = inttoptr i64 %arg to <4 x i64> addrspace(1)*
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%tmp2 = load <4 x i64>, <4 x i64> addrspace(1)* %tmp1, align 16
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store volatile <4 x i64> %tmp2, <4 x i64> addrspace(1)* undef
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #1
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attributes #0 = { convergent nounwind }
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attributes #1 = { nounwind readnone speculatable }
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