mirror of
https://github.com/Gericom/teak-llvm.git
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773ae62ff8
Summary: Support for i64 arguments (in register), return values and constants along with tests. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D72776
53 lines
1.6 KiB
C++
53 lines
1.6 KiB
C++
//===-- VEInstrInfo.h - VE Instruction Information --------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the VE implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_VE_VEINSTRINFO_H
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#define LLVM_LIB_TARGET_VE_VEINSTRINFO_H
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#include "VERegisterInfo.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#define GET_INSTRINFO_HEADER
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#include "VEGenInstrInfo.inc"
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namespace llvm {
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class VESubtarget;
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class VEInstrInfo : public VEGenInstrInfo {
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const VERegisterInfo RI;
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const VESubtarget &Subtarget;
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virtual void anchor();
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public:
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explicit VEInstrInfo(VESubtarget &ST);
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/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
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/// such, whenever a client has an instance of instruction info, it should
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/// always be able to get register info as well (through this method).
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///
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const VERegisterInfo &getRegisterInfo() const { return RI; }
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void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
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bool KillSrc) const override;
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// Lower pseudo instructions after register allocation.
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bool expandPostRAPseudo(MachineInstr &MI) const override;
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bool expandExtendStackPseudo(MachineInstr &MI) const;
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};
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} // namespace llvm
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#endif
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