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![]() The generic BaseMemOpClusterMutation calls into TargetInstrInfo to analyze the address of each load/store instruction, and again to decide whether two instructions should be clustered. Previously this had to represent each address as a single base operand plus a constant byte offset. This patch extends it to support any number of base operands. The old target hook getMemOperandWithOffset is now a convenience function for callers that are only prepared to handle a single base operand. It calls the new more general target hook getMemOperandsWithOffset. The only requirements for the base operands returned by getMemOperandsWithOffset are: - they can be sorted by MemOpInfo::Compare, such that clusterable ops get sorted next to each other, and - shouldClusterMemOps knows what they mean. One simple follow-on is to enable clustering of AMDGPU FLAT instructions with both vaddr and saddr (base register + offset register). I've left a FIXME in the code for this case. Differential Revision: https://reviews.llvm.org/D71655 |
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.. | ||
AsmParser | ||
Disassembler | ||
MCTargetDesc | ||
TargetInfo | ||
CMakeLists.txt | ||
Lanai.h | ||
Lanai.td | ||
LanaiAluCode.h | ||
LanaiAsmPrinter.cpp | ||
LanaiCallingConv.td | ||
LanaiCondCode.h | ||
LanaiDelaySlotFiller.cpp | ||
LanaiFrameLowering.cpp | ||
LanaiFrameLowering.h | ||
LanaiInstrFormats.td | ||
LanaiInstrInfo.cpp | ||
LanaiInstrInfo.h | ||
LanaiInstrInfo.td | ||
LanaiISelDAGToDAG.cpp | ||
LanaiISelLowering.cpp | ||
LanaiISelLowering.h | ||
LanaiMachineFunctionInfo.cpp | ||
LanaiMachineFunctionInfo.h | ||
LanaiMCInstLower.cpp | ||
LanaiMCInstLower.h | ||
LanaiMemAluCombiner.cpp | ||
LanaiRegisterInfo.cpp | ||
LanaiRegisterInfo.h | ||
LanaiRegisterInfo.td | ||
LanaiSchedule.td | ||
LanaiSelectionDAGInfo.cpp | ||
LanaiSelectionDAGInfo.h | ||
LanaiSubtarget.cpp | ||
LanaiSubtarget.h | ||
LanaiTargetMachine.cpp | ||
LanaiTargetMachine.h | ||
LanaiTargetObjectFile.cpp | ||
LanaiTargetObjectFile.h | ||
LanaiTargetTransformInfo.h | ||
LLVMBuild.txt |