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d6a7da80aa
llvm/test/DebugInfo/MIR/X86/live-debug-values-reg-copy.mir failed with EXPENSIVE_CHECKS enabled, causing the patch to be reverted in rG2c496bb5309c972d59b11f05aee4782ddc087e71. This patch relands the patch with a proper fix to the live-debug-values-reg-copy.mir tests, by ensuring the MIR encodes the callee-saves correctly so that the CalleeSaved info is taken from MIR directly, rather than letting it be recalculated by the PEI pass. I've done this by running `llc -stop-before=prologepilog` on the LLVM IR as captured in the test files, adding the extra MOV instructions that were manually added in the original test file, then running `llc -run-pass=prologepilog` and finally re-added the comments for the MOV instructions.
95 lines
3.9 KiB
C++
95 lines
3.9 KiB
C++
//===- ARMTargetFrameLowering.h - Define frame lowering for ARM -*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_ARM_ARMFRAMELOWERING_H
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#define LLVM_LIB_TARGET_ARM_ARMFRAMELOWERING_H
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/TargetFrameLowering.h"
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#include <vector>
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namespace llvm {
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class ARMSubtarget;
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class CalleeSavedInfo;
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class MachineFunction;
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class ARMFrameLowering : public TargetFrameLowering {
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protected:
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const ARMSubtarget &STI;
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public:
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explicit ARMFrameLowering(const ARMSubtarget &sti);
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/// emitProlog/emitEpilog - These methods insert prolog and epilog code into
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/// the function.
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void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
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void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
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bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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const std::vector<CalleeSavedInfo> &CSI,
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const TargetRegisterInfo *TRI) const override;
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bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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std::vector<CalleeSavedInfo> &CSI,
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const TargetRegisterInfo *TRI) const override;
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bool keepFramePointer(const MachineFunction &MF) const override;
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bool enableCalleeSaveSkip(const MachineFunction &MF) const override;
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bool hasFP(const MachineFunction &MF) const override;
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bool hasReservedCallFrame(const MachineFunction &MF) const override;
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bool canSimplifyCallFramePseudos(const MachineFunction &MF) const override;
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int getFrameIndexReference(const MachineFunction &MF, int FI,
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unsigned &FrameReg) const override;
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int ResolveFrameIndexReference(const MachineFunction &MF, int FI,
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unsigned &FrameReg, int SPAdj) const;
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void getCalleeSaves(const MachineFunction &MF,
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BitVector &SavedRegs) const override;
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void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs,
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RegScavenger *RS) const override;
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void adjustForSegmentedStacks(MachineFunction &MF,
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MachineBasicBlock &MBB) const override;
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/// Returns true if the target will correctly handle shrink wrapping.
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bool enableShrinkWrapping(const MachineFunction &MF) const override {
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return true;
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}
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bool isProfitableForNoCSROpt(const Function &F) const override {
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// The no-CSR optimisation is bad for code size on ARM, because we can save
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// many registers with a single PUSH/POP pair.
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return false;
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}
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private:
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void emitPushInst(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
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const std::vector<CalleeSavedInfo> &CSI, unsigned StmOpc,
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unsigned StrOpc, bool NoGap,
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bool(*Func)(unsigned, bool), unsigned NumAlignedDPRCS2Regs,
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unsigned MIFlags = 0) const;
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void emitPopInst(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
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std::vector<CalleeSavedInfo> &CSI, unsigned LdmOpc,
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unsigned LdrOpc, bool isVarArg, bool NoGap,
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bool(*Func)(unsigned, bool),
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unsigned NumAlignedDPRCS2Regs) const;
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MachineBasicBlock::iterator
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eliminateCallFramePseudoInstr(MachineFunction &MF,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI) const override;
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};
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} // end namespace llvm
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#endif // LLVM_LIB_TARGET_ARM_ARMFRAMELOWERING_H
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